Hao-Yi Lu

National Taiwan University

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Yu-Rui Chen

Chang Gung University

C. W. Liu

National Taiwan University

Wan-Hsuan Hsieh

National Taiwan University

Yu-Tsung Liao

National Taiwan University

Zefu Zhao

Fuzhou University

Yun-Wen Chen

National Taiwan University

Dai-Ying Lee

Macronix International (Taiwan)

Wei-Jen Chen

National Taiwan University

Ming-Hsiu Lee

Macronix International (Taiwan)

Yu-An Chen

National Yang Ming Chiao Tung University

Cooperative Institutions

National Taiwan University

Taiwan Semiconductor Manufacturing Company (Taiwan)

National Yang Ming Chiao Tung University

National Tsing Hua University

Taiwan Semiconductor Manufacturing Company (United States)

National Cheng Kung University

National Taipei University of Technology

University of Hong Kong

Institute of Electronics

Wuhan University of Technology

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0.18 µm BCD technology platform with best-in-class 6 V to 70 V power MOSFETs

Hsueh-Liang Chou P. Su Jacky C. W. Ng P. L. Wang Hao-Yi Lu

This paper presents a single BCD technology platform with high performance power devices at a wide range of operating voltages. The platform offers 6 V to 70 V LDMOS devices. All devices offer best-in-class specific on-resistance of 20 to 40 % lower than that of the state-of-the-art IC-based LDMOS devices and robustness better than the square SOA (safe-operating-area). Fully isolated LDMOS devices, in which independent bias is capable for circuit flexibility, demonstrate superior specific on-resistance (e.g. 11.9 mΩ-mm ² for breakdown voltage of 39 V). Moreover, the unusual sudden current enhancement appeared in the I _D -V _D saturation region of most of the high voltage LDMOS devices is significantly suppressed.

LDMOS

Robustness

10.1109/ispsd.2012.6229106

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Engineering HZO by Flat Amorphous TiN with 0.3nm Roughness Achieving Uniform c-Axis Alignment, Record High Breakdown Field (~10nm HZO), and Record Final 2Pr of 56 μC/cm² with Endurance > 4E12

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (2024)

Zefu Zhao Yu-Rui Chen Yu-Tsung Liao Yun-Wen Chen Wan-Hsuan Hsieh

10.1109/vlsitechnologyandcir46783.2024.10631450

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First Demonstration of Monolithic Self-aligned Heterogeneous Nanosheet Channel Complementary FETs with Matched V_T by Band Alignments of Individual Channels

2022 International Electron Devices Meeting (IEDM) (2023)

Chien-Te Tu Wan-Hsuan Hsieh Yu-Rui Chen Bo‐Wei Huang Yu-Tsung Liao

Monolithic 3D stacked Ge 0.9 Sn 0.1 nanosheet and Ge 0.75 Si 0.25 nanosheet complementary FETs with multiple P/N junction isolation by in-situ doped CVD epitaxy are experimentally demonstrated. Heterogeneous channels with common single work function metal gate structure are fabricated as a CMOS inverter with the matched V T and good voltage transfer characteristics. V T tuning is achieved individually by the band alignment of GeSi and GeSn for n-channel and p-channel, respectively, for the first time. The Hf 0.2 Zr 0.8 O 2 gate stacks with extremely high κ of 47 are integrated to enhance the I ON of CFET for high performance. The monolithic stacked heterogeneous complementary FETs without the need of wafer bonding, dielectric isolation, selective epitaxial growth, and dual work function metal can simplify the process for transistor 3D stacking.

Nanosheet

10.1109/iedm45741.2023.10413805

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WN_xC_y V_T Tuning of Split Gate Nanosheet CFETs with Dual Work Function Metals Achieving 0.93 V_T Match/Improved 0.24V Noise Margin/Record Gain of 61V/V

2021 IEEE International Electron Devices Meeting (IEDM) (2024)

Bo‐Wei Huang Chun-Yi Cheng Wan-Hsuan Hsieh Yu-Rui Chen Wei-Jen Chen

Nanosheet

10.1109/iedm50854.2024.10873325

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Uniform and Fatigue-Free Ferroelectric HZO with Record E_BD of 6.3MV/cm and Record Final 2P_r of $\boldsymbol{64}\mathbf{uC}/\mathbf{cm}^{2}$ at Record 5E12 Endurance Using Low Lattice Misfit (2.9%) $\boldsymbol{\beta}-\mathrm{W}$