qingkun li

Institute of Microelectronics

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Huaxiang Yin

Institute of Microelectronics

Renjie Jiang

Chinese Academy of Sciences

Lianlian Li

Institute of Microelectronics

Qingzhu Zhang

Chinese Academy of Sciences

Guanqiao Sang

Chinese Academy of Sciences

Meihe Zhang

Beijing Institute of Technology

Anyan Du

Chinese Academy of Sciences

Xuexiang Zhang

Chinese Academy of Sciences

Yunjiao Bao

Institute of Microelectronics

Lei Cao

National Marine Data and Information Service

Cooperative Institutions

Chinese Academy of Sciences

Institute of Microelectronics

University of Chinese Academy of Sciences

Chinese Academy of Science South America Center for Astronomy

Shandong University

Zhejiang University

Zhengzhou University

Harbin Medical University

National University of Singapore

Xuzhou Medical College

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Improved Subthreshold Characteristics of Epi-Silicon FinFET via Fin Surface Passivation Technologies

ECS Journal of Solid State Science and Technology (2024)

Wang Peng Guanqiao Sang Kun Yang Jiaxin Yao Lianlian Li

Abstract As demand for advanced integrated circuits (ICs) continues to grow, fin field-effect transistors (FinFETs) have remained highly influential in the IC market because of their mature fabrication process and powerful driving capabilities. However, the ion bombardment that occurs during the reactive ion etching (RIE) process used to form the fin structure increases the fin's surface roughness and results in a high interfacial state density (Dit), which hinders further improvement in the subthreshold swing (SS) of FinFETs. To overcome this issue, this study proposes two oxidative trimming methods for use on the fin structures to improve their interface quality. It is found that conventional thermal oxidation and low-temperature oxidation processes reduced the channel Dit by 73.31% vs. 71.17%, respectively. Furthermore, the corresponding SS values of the device improved to 72.76 and 71.72 mV/dec, respectively. The technical solutions proposed in this paper represent a promising approach for performance optimization of FinFETs and other advanced devices.

Passivation

Subthreshold conduction

Fin

Subthreshold slope

10.1149/2162-8777/ad8187

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Stacked Gate-All-Around Nanosheet Transistors with Full-Air-Spacers for Reducing Parasitic Capacitance to Improve Device and Circuit Performance

Microelectronics Journal (2024)

Lianlian Li Lei Cao Xuexiang Zhang qingkun li Zhenhua Wu

Nanosheet

Parasitic capacitance

Parasitic element

10.1016/j.mejo.2024.106535

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Stacked Si Nanosheets Gate-All-Around Transistors with Silicon-on-Nothing Structure for Suppressing Parasitic Effects and Improving Circuits’ Performance

ECS Journal of Solid State Science and Technology (2024)

Lianlian Li Lei Cao Xuexiang Zhang qingkun li Meihe Zhang

We propose a novel silicon-on-nothing (SON) structure with an air sub-fin for suppressing the parasitic channel effects on stacked Si nanosheets (NS) gate-all-around (GAA) transistors and a systematic investigation is carried out by 3D TCAD simulation. The SON structure could be fabricated using a backside selective etching technique. The proposed SON NSFETs with a designed air sub-fin structure demonstrates systematic advantages, including 40% off-state current reduction in the sub-channel, and 51.37% promotion for on-off current ratio (I ON /I OFF ) and 7.04% reduction in effective capacitance. Moreover, there is approximately 21.62% power reduction under the same frequency, and about 16.30% energy reduction under the same delay in 17-stage ring oscillators (ROs). The SON NSFETs-based 6T-SRAM exhibits decreased read time and write time by 14.66% and 67.53%, respectively, compared with those of the conventional GAA NSFETs-based 6T-SRAM.

10.1149/2162-8777/ad5106

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Citations (1)

COMBINED HEPATOCHOLANGIOCARCINOMA: UNRESOLVED POINTS. Minireview.

Authorea (Authorea) (2023)

sang guanqiao Xulei Qin Lei Cao qingkun li renjie jiang

In this paper, in order to improve the performance and reduce leakage of bulk low-temperature multi-layer SiGe/Si superlattice (SL) FinFETs, a p-type omage-shaped-channel (’Ω’-channel) SL FinFETs is realized by etching Si/Si0.7Ge0.3 triple-layer stacked structure in replace metal gate (RMG) module on the SOI substrate. In addition, a self-allied Ni0.9Pt0.1 silicide process and a low-thermal budget (≤ 400℃) integration were carried out on the ‘Ω’-channel SL FinFETs. The results demonstrate that the on-state current (Ion) is increased by 5.5 times (from 78 μA/μm to 429 μA/μm) and the Ioff decreases by 78.8% (from 5.2 × 10-3 μA/μm to 1.1 × 10-3 μA/μm) compared with those of traditional bulk SL FinFETs.

Metal gate

Leakage (economics)

10.22541/au.169720772.25363889/v1

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