Bala Haran

Applied Materials (United States)

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Branko N. Popov

University of South Carolina

J. Demarest

IBM (United States)

Dechao Guo

Xi'an Jiaotong University

Mukesh Khare

Indian Institute of Technology Delhi

N. Loubet

IBM (United States)

H. Bu

University of Chinese Academy of Sciences

S. Mehta

GlobalFoundries (United States)

B. Doris

IBM (United States)

Veeraraghavan Basker

Applied Materials (United States)

J. Li

North China Electric Power University

Cooperative Institutions

IBM (United States)

359

GlobalFoundries (United States)

172

IBM Research - Thomas J. Watson Research Center

133

Albany Molecular Research (United States)

106

GlobalFoundries (Germany)

Applied Materials (United States)

IBM Research - Austin

University at Albany, State University of New York

Samsung (United States)

Samsung (South Korea)

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Tungsten and cobalt metallization: A material study for MOL local interconnects

V. Kamineni M. Raymond S. Siddiqui Frank W. Mont Stan Tsai

Middle-of-the-line (MOL) interconnect and contact resistances represent significant impacts to high-end IC performance at ≤ 10 nm nodes. CVD W-based metallization has been used for all nodes since the inception of damascene. However, it is now being severely challenged due to limited scaling of the traditional PVD Ti/CVD TiN barrier and ALD nucleation layers. This study reports the use of alternate barriers, along with metal-to-metal contact interface cleans, to reduce contact resistance for W-based MOL metallization. As well, we report the first use of Co metal for MOL contacts and local interconnects, with successful integration below a Cu BEOL dual damascene V0/M1 module. Metal line resistances are compared among the various options, and the challenges with each option are highlighted.

Copper interconnect

Contact resistance

Electromigration

10.1109/iitc-amc.2016.7507698

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Citations (53)

Study of polypyrrole graphite composite as anode material for secondary lithium-ion batteries

Journal of Power Sources (2002)

Basker Veeraraghavan Jason Paul Bala Haran Branko N. Popov

Polypyrrole

10.1016/s0378-7753(02)00105-2

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Citations (148)

Pipeline Climbing Robot for Scaling of Gas Leakage Detection

2022 6th International Conference on Intelligent Computing and Control Systems (ICICCS) (2023)

S. Sivarajeswari S. Sai Isha K. Vanitha S. Reshma G. Magendran

Leakage is the major problem in every pipeline network. All over the world leakage is the main issue on the globe, Pipeline leakage is the primary cause of losses in oil, gas and water. Sometimes harmful gasses leakage in pipelines causes health issues. The pipeline climbing robot for gas leakage will detect the leaks and find the location, where the robot will go to the particular location and produce a buzzer sound. A small mobile robot is designed to identify the gas leakage in the pipeline. The mobile robot moves automatically when it senses the leakage of gas in the pipeline. A buzzer keeps ringing till the user identifies the problem. This pipeline climbing robot identifies the leaks in the pipeline like harmful places that cannot be reached by humans in that situation. This pipeline climbing robot plays a major role in detecting gas leakage in any condition.

Buzzer

Leakage (economics)

Climbing

10.1109/iciccs56967.2023.10142557

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Citations (0)

10nm FINFET technology for low power and high performance applications

Dechao Guo Huiling Shang Keehong Seo Bala Haran T. Standaert

In this paper, we present a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrates. A 0.053um ² SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limits. Multi-workfunction (MWF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by Random Dopant Fluctuation (RDF) from channel dopants.

Noise margin

Degradation

10.1109/icsict.2014.7021207

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Citations (9)

Novel Logic & SRAM Interconnect Design for Advanced Complementary FET (CFET) Based Technology Nodes

2021 IEEE International Electron Devices Meeting (IEDM) (2024)

Ashish Pal Pratik B. Vyas S. Dağ Gregory Costrini B. Colombeau

10.1109/iedm50854.2024.10873398

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Citations (0)

Corrosion Protection of Steel Using Nonanomalous Ni-Zn-P Coatings

Journal of The Electrochemical Society (2003)

Basker Veeraraghavan Bala Haran Swaminatha P. Kumaraguru Branko N. Popov

A novel technique for obtaining nonanomalous Ni-Zn-P coatings with high Ni content (74 wt % as compared to 15-20 wt % in the conventional plating method) has been developed. These coatings show promise as a replacement for Cd in sacrificially protecting steel. Ni-Zn-P coatings were deposited using an electroless method from a solution containing complexing agent and ammonium chloride. Varying the concentration of in the bath controls the final amount of Zn in the deposit. The Zn content in the coating was optimized based on the corrosion resistance of the final deposit. Coatings with 16.2 wt % Zn were found to display a potential of vs. SCE that is more electronegative to steel and hence can be used as a sacrificial coating for the protection of steel. Deposition parameters like pH and temperature have been optimized based on composition of the coating and the surface morphology. Corrosion studies in corroding media show that Ni-Zn-P coatings obtained using the electroless method show a higher barrier resistance and better stability as compared to cadmium coatings. © 2003 The Electrochemical Society. All rights reserved.

Plating (geology)

Deposition

Conversion coating

Carbon steel

10.1149/1.1556015

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Citations (47)

Metal Wet Recess Challenges and Solutions for beyond 7nm Fully Aligned Via Integration

B. Peethala Devika Sil Benjamin D. Briggs Deb Kumar Rath Nicholas A. Lanzillo

The Fully aligned via scheme (FAV) is known to mitigate the via misalignment issues that drive a lower Vmax and limits the contact area between the via and the underlying line. Even though the overall benefits of FAV are well known, the key detractors and their contributions are not well understood. One of the key challenges in FAV integration is the need to create of topography which can be either achieved by recessing the metal lines or by selective insulator deposition. Wet recess process has been promising for enabling downstream integration learning of conformal cap deposition, ultra low-k gap-fill, and via landing on recessed area. In this paper wet recess challenges for topography creation and key process improvements that improve the resistance distribution are discussed.

Deposition

10.1109/iitc51362.2021.9537484

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Citations (2)

Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm

Symposium on VLSI Technology (2019)

Ruilong Xie Chanro Park Rena M. Conti Robert R. Robison Huimei Zhou

We demonstrate a novel self-aligned gate contact (SAGC) scheme with conventional oxide/nitride materials that allows superior process integration for scaling while simplifying the SRAM cross-couple wiring. We show that the key feature to avoid both gate-contact (CB) to source-drain local interconnect (LI) shorts and the LI-contact (CA) to gate shorts is the shape of the LI cap. A trapezoid-shaped oxide (SiO ₂ ) LI cap with an appropriate taper angle eliminates shorting between the contacts in the gate and source-drain region. We further demonstrate that this oxide LI cap is fully compatible with Cobalt (Co) metallization with a novel selective tungsten (W) growth process. Additionally, this process enables the SRAM cross-couple (XC) in the same metallization level, eliminating the need for an upper level wiring and greatly simplifying routing in the SRAM cell.

Metal gate

10.23919/vlsit.2019.8776492

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Citations (5)

Material, Process and System Level Analysis for Parasitic Reduction of Next Generation Logic Technology in Conjunction with Backside Power Delivery

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (2024)

Ashish Pal S. Dağ Pratik B. Vyas Gregory Costrini V H Prasad Reddy

Conjunction (astronomy)

10.1109/vlsitechnologyandcir46783.2024.10631438

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Citations (0)

Development of First Principles Capacity Fade Model for Li-Ion Cells

Journal of The Electrochemical Society (2004)

Premanand Ramadass Bala Haran Parthasarathy Gomadam Ralph E. White Branko N. Popov

A first principles-based model has been developed to simulate the capacity fade of Li-ion batteries. Incorporation of a continuous occurrence of the solvent reduction reaction during constant current and constant voltage (CC-CV) charging explains the capacity fade of the battery. The effect of parameters such as end of charge voltage and depth of discharge, the film resistance, the exchange current density, and the over voltage of the parasitic reaction on the capacity fade and battery performance were studied qualitatively. The parameters that were updated for every cycle as a result of the side reaction were state-of-charge of the electrode materials and the film resistance, both estimated at the end of CC-CV charging. The effect of rate of solvent reduction reaction and the conductivity of the film formed were also studied. © 2004 The Electrochemical Society. All rights reserved.

Fade

Exchange current density

Capacity loss

State of charge

10.1149/1.1634273

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Citations (720)