Young-Su Kwon

Electronics and Telecommunications Research Institute

Author Statistics

Papers

Citation

H-Index

i-10 index

Research Trends

Author Order

Document Type

Co-Authors

Chong‐Min Kyung

Korea Advanced Institute of Science and Technology

Jinho Han

Electronics and Telecommunications Research Institute

Chun‐Gi Lyuh

Electronics and Telecommunications Research Institute

Minseok Choi

Soongsil University

Nak-Woong Eum

Electronics and Telecommunications Research Institute

Yong Cheol Peter Cho

Electronics and Telecommunications Research Institute

Sang-Joon Nam

General Department of Preventive Medicine

In‐Cheol Park

Korea Advanced Institute of Science and Technology

Byoung-Woon Kim

Sunchon National University

Jaehoon Chung

Electronics and Telecommunications Research Institute

Cooperative Institutions

Korea Advanced Institute of Science and Technology

Electronics and Telecommunications Research Institute

Samsung (South Korea)

Seoul National University

Korea University

Genentech

Sungkyunkwan University

Soongsil University

Kyungpook National University

Pusan National University

Author Statistics

Papers

Citation

H-Index

i-10 index

Research Field

Aldebaran4コアに基づく仮想SoCプラットフォーム【Powered by NICT】

IEEE Conference Proceedings (2016)

Jae‐Jin Lee Young-Su Kwon

Source

Cite

Citations (0)

DQ and DQS Receiver for HBM3 Memory Interface with DFE Offset Calibration

2022 19th International SoC Design Conference (ISOCC) (2023)

Sujin Park Young-Deuk Jeon Yi-Gyeong Kim Minhyung Cho Jinho Han

This paper describes data (DQ) and data strobe (DQS) receiver for the HBM3 memory interface. The proposed DQ receiver based on a decision feedback equalizer (DFE) optimizes the eye-opening by using DFE offset calibration. Also, the area of the DQ receiver can be reduced by combining amplification, DFE control, and offset calibration in the preamplifier at once. The proposed DQS receiver uses the duty-cycle calibration and preamble period correction and can process an 8Gb/s signal without preamble error.

Preamble

Preamplifier

Duty cycle

10.1109/isocc59558.2023.10396021

Cite

Citations (0)

Partial access conflict-relieving programmable address shuffler for parallel memory system in multi-core processor

Microprocessors and Microsystems (2009)

Young-Su Kwon Nak-Woong Eum

Shuffling

Memory map

Memory architecture

10.1016/j.micpro.2009.10.002

Cite

Citations (3)

Design and Analysis of Redistribution Layer Interposer Channel Considering Signal Integrity for High Bandwidth Memory Module

Jiwon Yoon Hyunwook Park Hyunwoo Kim Boogyo Sim Jonghyun Hong

In this paper, we designed and analyzed redistribution layer (RDL) interposer channels for high bandwidth memory (HBM) module. The physical dimensions and material properties were designed based on recent RDL process technology. We analyzed the electrical performance of the RDL interposer channels in terms of insertion loss and far-end crosstalk (FEXT) with comparison to silicon interposer. To verify the performance of RDL interposer channels, eye diagram simulation was conducted based on the HBM3 setup conditions. Conventional RDL interposer show improved performance in terms of IL, but shows significant FEXT at high frequencies. From eye diagram of interposer channels, RDL show high eye distortion due to the composite effect of crosstalk and voltage ringing. As a future projection, RDL interposer was designed and analyzed considering the rise in maturity of RDL based process. As a result, we have shown that with future advances in RDL fabrication technology, RDL interposer channels can successfully be utilized for HBM3 applications at a data rate of 6.4 Gb/s.

Interposer

10.1109/epeps58208.2023.10314927

Cite

Citations (1)

SCATOMi : Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture

Proceedings of the IEEK Conference (2003)

Young-Su Kwon Chong-Min Kyung

Source

Cite

Citations (0)

MetaCore: an application-specific programmable DSP development system

IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2000)

Jin-Hyuk Yang Byoung-Woon Kim Sang-Joon Nam Young-Su Kwon Dae-Hyun Lee

This paper describes the MetaCore system which is an application-specific instruction-set processor (ASIP) development system targeted for digital signal processor (DSP) applications. The goal of the MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost, and design turnaround time. The MetaCore system consists of two major design stages: design exploration and design generation. In the design exploration stage, MetaCore system accepts a set of benchmark programs and structural/behavioral specifications for the target processor and estimates the hardware cost and performance for each hardware configuration being explored. Once a hardware configuration and instruction set are chosen, the system helps generate the target processor design in the form of hardware description language (HDL) along with the application program development tools such as C compiler, assembler, and instruction set simulator. The effectiveness of the MetaCore system was verified with a successful design of MDSP-II, a programmable DSP processor targeted for mobile communication.

Benchmark (surveying)

Application-specific instruction-set processor

10.1109/92.831437

Cite

Citations (24)

Automatic generation of software/hardware co-emulation interface for transaction-level communication

Young‐Il Kim Ki-Yong Aim Heejun Shim Wooseung Yang Young-Su Kwon

This paper presents a methodology for generating interface of a co-emulation system where processor and emulator execute testbench and design unit, respectively while interacting with each other. To reduce the communication time between the processor and emulator, data transfers are performed in transaction level instead of signal level. To do this, transactor should be located near the DUT mapped on the hardware emulator. Consequently transactor is described in a synthesizable way. Moreover, the transactor design depends on both emulator system protocol and DUT protocol. Therefore, transactor description would not only be time-consuming but also error-prone task. Based on the layered architecture, we propose an automated procedure for generating co-emulation interface from platform-independent transactor. We have also discussed about the practical issues on multiple channel and clock skew problem.

Interface (matter)

Hardware emulation

Device under test

10.1109/vdat.2005.1500054

Cite

Citations (4)

Simulation acceleration of transaction-level models for SoC with RTL sub-blocks

Jae-Gon Lee Wooseung Yang Young-Su Kwon Young-Il Kim Chong‐Min Kyung

This paper presents an optimized channel usage between simulator and accelerator when the simulator models transaction-level SoC while accelerator models RTL sub-blocks. Conventional simulation accelerators synchronize the progresses of simulator and accelerator at every simulation time, which results in poor performance by splitting transactions on the simulator-to-accelerator channel into pieces. Occasional synchronization with predictions and recoveries makes it possible to merge multiple transfers yielding substantial performance gain compared to the conventional method.

10.1145/1120725.1120921

Cite

Citations (6)

Quad-core media processor SoC with implicative dynamic parallel programming model

Young-Su Kwon Bontae Koo Nak-Woong Eum

The advancement of process technology enables the integration of multiple cores featuring the parallel processing with low operating energy and efficient resource utilization in embedded media processors. We propose mobile media processor SoC integrating RISC core and quad-core data processing engines with shared array of memory modules. The implicative dynamic parallel programming model dynamically distributes the programmer-specified parallelizable functions into multiple cores. The experimental result with parallelized audio processing algorithm on FPGA platform shows the effectiveness of the proposed processor SoC.

Programmer

Multi-core processor

Parallelizable manifold

10.1109/icce.2009.5012261

Cite

Citations (0)

TPL2 kinase action and control of inflammation

The Journal of Immunology (2020)

Daqi Xu Young-Su Kwon Kate Senger Victoria C. Pham Eugene Varfolomeev

Abstract Tumor progression locus 2 (TPL2; also known as MAP3K8) is a mitogen-activated protein kinase (MAPK) kinase kinase (MAP3K) that phosphorylates the MAPK kinases MEK1 and MEK2 (MEK1/2), which, in turn, activates the MAPKs extracellular signal–regulated kinase 1 (ERK1) and ERK2 (ERK1/2). We describe an additional conserved and critical role for TPL2 in mediating the effector functions of myeloid cells including neutrophils, macrophages, and microglia through the activation of the p38 MAPK signaling pathway. Gene expression profiling and functional studies of neutrophils and monocytes revealed a MEK1/2-independent branch point downstream of TPL2 in neutrophils. Genetic ablation of the catalytic activity of TPL2 or therapeutic intervention with TPL2-specific inhibitors reduced inflammatory responses in vitro and in vivo. Besides myeloid cells, TPL2 also plays critical roles in fibroblast synoviocytes, indicating a potential role in rheumatoid arthritis via stromal cells.

ASK1

10.4049/jimmunol.204.supp.152.3

Cite

Citations (0)