Yohei Matsumoto

Hitachi (Japan)

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Hanpei Koike

National Institute of Advanced Industrial Science and Technology

Masakazu Hioki

National Institute of Advanced Industrial Science and Technology

Takashi Kawanami

Kanazawa Institute of Technology

Toshiyuki Tsutsumi

Meiji University

Toshihiro Sekigawa

National Institute of Advanced Industrial Science and Technology

Tadashi Nakagawa

Tohoku University

A. Masaki

Nippon Foundation

Takashi Yokota

Utsunomiya University

Takeshi Ohkawa

Kumamoto University

Kanemitsu Ootsu

Utsunomiya University

Cooperative Institutions

Hitachi (Japan)

Tohoku University

The University of Tokyo

Kyoto University

Osaka University

National Institute of Advanced Industrial Science and Technology

Gifu Pharmaceutical University

Tokyo University of Marine Science and Technology

Kyushu Institute of Technology

Hokkaido University

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ChemInform Abstract: The Novel Preparation Methods of 5-Substituted Methyl-1-azabicyclo[3.3.0]octane.

ChemInform (1998)

Mitsuru Oka Kunihisa Baba Tomomi Suzuki Yohei Matsumoto

Abstract ChemInform is a weekly Abstracting Service, delivering concise information at a glance that was extracted from about 100 leading journals. To access a ChemInform Abstract of an article which was published elsewhere, please select a “Full Text” option. The original article is trackable via the “References” option.

10.1002/chin.199814112

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FPGAs with Multidimensional Switch Topology(VLSI Systems)

IEICE Transactions on Information and Systems (2005)

Yohei Matsumoto A. Masaki

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Citations (1)

ChemInform Abstract: 3‐Vinylcoumarins and 3‐Vinylchromenes as Dienes. Application to the Synthesis of 3,4‐Fused Coumarins and Chromenes.

ChemInform (1992)

T. MINAMI Yohei Matsumoto Shuichi Nakamura Shinichiro Koyanagi Masahiko Yamaguchi

10.1002/chin.199228062

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Built-in self-test for multiple CLB faults of a LUT type FPGA

Noriyoshi Itazaki Fumirou Matsuki Yohei Matsumoto K. Kinoshita

A new Built-in Self Test (BIST) method for multiple configurable logic block (CLB) faults of SRAM-Look-Up-Table (LUT) type FPGA is reported. In this method, self test is performed concurrently for every test block containing eight CLBs. Faulty FPGA which includes up to five faulty CLBs in one test block can be detected completely even if each faulted CLB includes unlimited number of faults.

Lookup table

Logic block

Built-in self-test

Table (database)

10.1109/ats.1998.741624

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Citations (12)

A HW/SW Cooperative System Design of Stabilization Processing of Images from Networked Cameras for the Realization of an Automatic Watch System for Safe Navigation

IEICE Technical Report; IEICE Tech. Rep. (2015)

Takeshi Ohkawa Yohei Matsumoto Inagawa Manabu Uetake Daichi Fusegi Mayu

Realization (probability)

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ChemInform Abstract: Reactions of Xanthinium N(7)‐Ylides with Olefinic Dipolarophiles.

ChemInform (1987)

Mikio Hori Tadashi Kataoka Hiroshi Shimizu Eiji Imai Yohei Matsumoto

Abstract Reaction of the respective methylides from the xanthinium salts (I) with the olefinic dipolarophiles (II), (VI) yields the adducts (III), (VII).

Ylide

10.1002/chin.198741245

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Experimental Study of Acquisition Support for Career Consulting Skill Using Physiological Information(2)

情報処理学会研究報告(Web) (2016)

Maki Arame Yohei Matsumoto Matsumoto Kazushige

Information technology consulting

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Development of a CAD tool for 3D-FPGAs

Naoto Miyamoto Yohei Matsumoto Hanpei Koike Tadayuki Matsumura Kenichi Osada

This paper presents a newly developed computer-aided design (CAD) tool for 3-dimensional field programmable gate arrays (3D-FPGAs). With this tool, primary inputs/outputs (I/Os) are packed in the configurable logic blocks (CLBs) and placed all over the 3D-FPGA. Moreover, rectangular parallelepiped confinement (RPC) and A-star (A*) search algorithms are applied to perform 3D routing, which is about 9.0 times faster than the one not introducing the algorithms, without degrading the routing quality.

10.1109/3dic.2010.5751458

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Citations (8)

FPGAs with multidimensional mesh topology

Yohei Matsumoto Hanpei Koike A. Masaki

In a traditional 2-D field-programmable gate array (FPGA), the number of routing switches increases as the number of logic gates increases, and thereby causes a decrease in the logic density. DeHon et al. demonstrated that a tree-based FPGA they proposed resolves this problem and requires only a constant number ofswitches per gate without any relation to the total number of gates. This paper presents that a multidimensional FPGA that exploits the multidimensional mesh topology also achieves asymptotically identical area efficiency to that of a tree-based FPGA. We model a multidimensional FPGA as a simple extension of the traditional 2-D and 3-D FPGAs, and realize it by embedding it onto a 2-D chip. We show a multidimensional FPGA can be embedded onto a 2-D chip with no critical increase in the amount of metal wiring. Although our embedding method causes a gap between the lengths of wire segments in different axial directions, a multidimensional FPGA indicates lower interconnection delay than a 2-D FPGA. We show that the speed advantage of a 4-D FPGA compared with a 2-D FPGA extends along with further integration and scaling of semiconductor devices by predicting maximum and average net delays.

Gate array

10.1145/1117201.1117234

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Speed improvement of FPGA by mixing multiple‐gate‐width routing switches

Electronics and Communications in Japan (Part III Fundamental Electronic Science) (2005)

Yohei Matsumoto A. Masaki

Abstract In comparison with ASIC, FPGA is slower in speed and has a smaller logic size that can be integrated. The main cause is the routing switches. Optimization of the gate width of the transistors used is important. Previously, a single gate width has been assumed for all of the path transistors in the optimization. In the present research, a structure is conceived in which multiple gate widths are mixed. The operating speed is increased by about 20% relative to conventional structures. © 2005 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 88(7): 14–22, 2005; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/ecjc.20154

Application-specific integrated circuit

Gate array

10.1002/ecjc.20154

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Citations (1)