J.F. Lin

United Microelectronics (Taiwan)

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J. Y. Wu

United Microelectronics (Taiwan)

T.C. Tsai

United Microelectronics (United States)

Chia-Lin Hsu

United Microelectronics (Taiwan)

Wen‐Chin Lin

National Taiwan Normal University

W. S. Sie

United Microelectronics (Taiwan)

H. K. Hsu

United Microelectronics (Taiwan)

Huan-Chu Huang

United Microelectronics (Taiwan)

C. L. Yang

Fujian Medical University

Chrong-Jung Lin

National Tsing Hua University

Jerander Lai

Southern Taiwan Science Park

Cooperative Institutions

United Microelectronics (Taiwan)

United Microelectronics (United States)

Applied Materials (United States)

National Yang Ming Chiao Tung University

National Cheng Kung University

Taiwan Semiconductor Manufacturing Company (Taiwan)

National Tsing Hua University

Applied Materials (Germany)

Industrial Technology Research Institute

National Taiwan University

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The P2P Live Media Streaming Technology in Distance Teaching Platform

International Conference on Information Science and Applications (2011)

Yun‐Sheng Yen Yu-Kai Chang J.F. Lin Nen-Fu Huang

Distance learning uses the network digital system to send messages point-to-point or point-to-multipoint. Presently, distance learning has gained remarkable results in universities and colleges. This paper experiments the operation of P2P Live Media Stream, a distance video system based on P2P structure. In addition, we also compare it with Co-Life Video Conferencing System developed by the National Center for High-Performance Computing and Marratech Online Video Conferencing System developed by a subsidiary company of Google. The comparisons focus on the smoothness of video signals, stability, connection recovery and transmission situations. We prove that P2P Live Media Stream is an ideal and feasible system which can be used in campuses. Furthermore, it combines all kinds of video teaching modes and benefits the teaching diversity in campuses.

Videoconferencing

Live Streaming

Smoothness

Video Streaming

10.1109/icisa.2011.5772363

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Citations (1)

Wafer extreme-far edge related study in BEOL (Back-End-of-Line) including BEOL chemical mechanical polishing at 28nm technology node and beyond

Yu‐Min Lin Shu-Hao Hsu L. C. Hsu C. H. Hsu Chien Liang Wu

In this study, a robust Cu chemical mechanical polishing (CMP) process with better Cu polishing profile, lower defectivity and tighten metal line sheet resistance (Rs) control has been evaluated on a dual wafer polisher to meet the CuCMP process criteria at 28nm node. As the metal line width kept shrinking to 28nm node, the CMP correlated performance such as metal line resistance which resulted from the CMP induced surface erosion and dishing, defect resulted from barrier polishing and reliability. However, as the parameter was optimized to gain better performance, others related phenomenon would also be induced especially at wafer extremely far edge. The related study of wafer extremely far edge metrology issues will be introduced: First part is the description of wafer extremely far edge metrology issue. Accordingly, the hypothesis and the partition of wafer extremely far edge metrology issue will be introduced, such as the increasing Cu density which is influenced by pattern deformation around wafer extremely far edge and the different polished wafer extremely far edge topography resulted from different polishing slurry selections. Meanwhile, the metrology issue results from several processes such as Cu plating, photoresist patterning, CMP, etc. Based on mentioned studies, the wafer extremely far edge metrology issues can be solved by implementing suitable Cu plating, lithography and CMP process.

Chemical Mechanical Planarization

Plating (geology)

10.1109/icpt.2014.7017284

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Citations (1)

Single Wafer Selective Silicon Nitride Removal with Phosphoric Acid and Steam

Diffusion and defect data, solid state data. Part B, Solid state phenomena/Solid state phenomena (2014)

Ted Guo Wesley M. Yu C. C. Chien Euing Lin N.H. Yang

A single wafer silicon nitride (SiN) selective etch process with an etch rate greater than 80A/min of low-pressure chemical vapor deposited (LPCVD) SiN has been developed. Previous work with a similar single wafer system utilized a mixture of sulfuric acid, phosphoric acid and steam to achieve a high SiN etch rate [1]. The process in this work relies on phosphoric acid and steam for a high SiN etch rate. In both of these applications, addition of steam doubles the SiN etch rate. The single wafer system utilizes a closed chamber design with integrated spray bar to uniformly dispense hot phosphoric acid and steam onto the wafer surface achieving within wafer non-uniformities of less than 3%. Rinsing and drying of the phosphoric acid from the wafer surface occurs in the same chamber (dry in/dry out) providing a stable, haze free wafer. Figure 1 contains a schematic of the phosphoric acid delivery and single wafer system.

Phosphoric acid

Die preparation

10.4028/www.scientific.net/ssp.219.97

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Citations (2)

Investigation of aluminum film properties and microstructure for replacement metal gate application

Microelectronic Engineering (2013)

Rao Huang T.C. Tsai Welch Lin Huan-Chu Huang Ming‐Shih Tsai

Chemical Mechanical Planarization

Pinhole (optics)

Deposition

Electromigration

10.1016/j.mee.2013.02.016

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Citations (8)

Reliability Test Guidelines for a 0.18 µm Generation Multi-Oxide CMOS Technology for System-on-Chip Applications

Japanese Journal of Applied Physics (2003)

Shang-Jr Chen Ching-Chung Lin Steve S. Chung J.F. Lin Chih-Hsiun Chu

With an increase of power dissipation and integrated-circuit (IC) density in system-on-a-Chip (SoC), it is not sufficient to determine complementary metal-oxide-semiconductor (CMOS) device lifetime by merely monitoring stress-bias conditions, such as hot-carrier (HC) stress. The temperature effect is a significant factor affecting the device lifetime. More and more evidence has been reported which indicates the significance of the temperature effect on device reliability, particularly the negative bias and temperature instability (NBTI) in p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs). In this work, a complete test of seven kinds of stress conditions which affect device lifetime will be carried out for 0.18 µm generation SoC technology CMOS devices with multiple oxide thicknesses and multiple applied biases. Based on these results, we provide guidelines for next-generation SoC CMOS technology. In nMOSFETs, the temperature effect is weak and therefore conventional hot carrier (HC) stress (i.e., maximum substrate current stress, IB,max) at room temperature dominates the device lifetime. However, in pMOSFETs, the temperature effect is critically important for determining the device lifetime. It was found that NBTI-like HC stress (VG=VD at high-T) has been shown to dominate the device lifetime for both 0.18 µm and 0.35 µm pMOSFETs. Furthermore, the NBTI effect will become more pronounced with the device channel length scaling.

10.1143/jjap.42.1928

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Citations (2)

A comprehensive process engineering on TDDB for direct polishing ultra-low k dielectric Cu interconnects at 40nm technology node and beyond

International Reliability Physics Symposium (2011)

Wen‐Chin Lin T.C. Tsai H. K. Hsu Jack Lin W. C. Tsao

The failure ratios of the three typical time-dependent dielectric breakdown (TDDB) failure modes, including top interface, sidewall and bottom corner areas, have been identified for a direct polishing ultra low k (ULK) dielectric Cu back-end-of-line (BEOL) structure at 40nm node. The Cu surface roughness of the metal lines, and the adhesion and thickness of the metal capping layers are strongly correlated to the top interface failure mode. The dielectric constant of the ULK and the concentration of the aluminum-doped Cu (CuAl) seed layer could be related to the sidewall failure mode. The bottom corner failures are induced by inappropriate Cu barrier re-sputter processes. In this study, the TDDB reliability performance can be effectively improved by evaluating a post-Cu chemical mechanical polishing (Cu CMP) cleaning process with smooth Cu surface roughness, developing a better step coverage with multi-layer capping layer, using a slightly higher dielectric constant ULK film, replacing a conventional pure Cu with a CuAl seed layer and optimizing the Cu barrier layer deposition process. The lifetime of the TDDB can be significantly improved over three orders (larger than 10000 years) as implementing an optimized integrated Cu with ULK BEOL structures at 40nm technology node.

Chemical Mechanical Planarization

Barrier layer

Low-k dielectric

Dielectric strength

10.1109/irps.2011.5784470

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Citations (6)

Evaluation of aluminum film properties and microstructure for replacement metal gate application at 28nm technology node

Rao Huang Yeh-Hsin Hsien T.C. Tsai Welch Lin Huan-Chu Huang

The fundamental film properties and microstructures of the different aluminum (Al) metal layers are evaluated to fabricate a replacement metal gate (RMG) device for the high-k metal gate (HKMG) application at 28 nm node. A PVD Al fill-in metal deposition process, called one step hot Al (HAL), was found the resistivity increases with increasing the thickness of the Ti wetting layer. The higher pinhole density with the preferred (111) crystal orientation in the HAL layers indicate the film properties with lower reflectivity, higher resistivity and lower removal rate of the Al chemical mechanical polishing (AlCMP). In contrast, the other PVD Al deposition approach, called two steps cold hot Al (CHAL), was identified to possess lower resistivity and higher reflectivity without pinhole structures than the HAL. The smaller grain sizes with the preferred (220) orientation in the CHAL could effectively prevent the formation of pinhole and enhance the removal rate of the AlCMP. The non-uniform with crystallized TiAl3 phase detected in the bottom of the as-deposited HAL and CHAL films could obviously impact the removal rate of the AlCMP. An optimized CHAL fill-in metal deposition process with a larger than 40 Å Ti wetting layer are needed to simultaneously meet the process requirements of the Al gapfill and AlCMP planarization for achieving a reliable RMG structures.

Pinhole (optics)

Chemical Mechanical Planarization

Deposition

Electromigration

10.1109/iitc.2011.5940271

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Citations (1)

Wet Etch Rate Behavior of Poly-Si in TMAH Solution at Various Ambient Gas Conditions

Diffusion and defect data, solid state data. Part B, Solid state phenomena/Solid state phenomena (2014)

Euing Lin Ted Guo C. C. Chien Myeong‐Soo Chang Wesley M. Yu

As the demand for greater speed in semiconductor devices continues, a typical method of increasing charge mobility is to maximise the silicon strain at the depletion region in p-type transistors through the implementation of “Sigma Cavity” structures in the bulk silicon on either side of the gate structure. These structures, when filled, exhibit a uniaxial strain in the depletion region thus, increasing the charge transport speed [1]. The shape of the Sigma Cavity structure is important in maximising the strain in this region, thus strict control of the shape dimensions is imperative to the electrical performance of the device.

Depletion region

Strain (injury)

10.4028/www.scientific.net/ssp.219.78

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Citations (1)

Effects of Cu surface roughness on TDDB for direct polishing ultra-low k dielectric Cu interconnects at 40nm technology node and beyond

Microelectronic Engineering (2011)

Wen‐Chin Lin Jack Lin T.C. Tsai Chia-Lin Hsu C. C. Liu

Chemical Mechanical Planarization

Dielectric strength

Low-k dielectric

10.1016/j.mee.2011.04.057