Accurate and flexible simulation methods may be used to further a researcher's understanding of how complex resist effects influence the patterning of critical structures. In this work, we attempt to gain insight into the behavior of a state-of-the-art EUV resist through the use of stochastic resist modeling. The statistics of photon and molecule counting are discussed. The acid generation mechanism at EUV is discussed. At lambda = 13.5 nm, the acid generation mechanism may be similar to that found in electron beam resists: acid generators are hypothesized to be activated by secondary electrons yielded by ionization of the resist matrix by high-energy EUV photons, suggesting that acid generators may be activated some distance from the absorption site. A discrete, probabilistic ionization and electron scattering model for PAG conversion at EUV is discussed. The simulated effect of resist absorbance at EUV upon doseto- size and line-width roughness is shown. The model's parameterized fit to experimental data from a resist irradiated EUV are shown. Predictions of statistical resist responses such as CD distribution and line-width roughness are compared with experimental data.
In advanced photolithography process for manufacturing integrated circuits, the critical pattern sizes that need to be printed on wafer are much smaller than the wavelength. Thus, source optimization (SO) techniques play a critical role in enabling a successful technology node. However, finding an appropriate illumination configuration involves intensive computation simulations. EDA vendors have been developing the pixelated source optimization tools that co-optimize both source and mask for a set of patterns. As an alternative approach, we have introduced design of experiments (DOE) methodology for parameterized source optimization to minimize computation efforts while achieving comparable CDU control for given design patterns. In this paper, we present a Response Surface Methodology (RSM) that simplifies the response function and achieves the optimization goal on multiple responses. Results have shown that the optimal input settings identified by this approach are comparable with the pixelated source optimization results.
As Critical Dimension (CD) sizes decrease for 32 nm node and beyond, resist loss increases and resist patterns become more vulnerable to etching failures. Traditional OPC models only consider 2D contours and neglect height variations. Rigorous resist simulators can simulate a 3D resist profile but they are not fast enough for correction or verification on a full chip. However, resist loss for positive tone resists is mainly driven by optical intensity variations which are accurately modeled by the optical portion of an OPC model. In this article, we show that a CalibreTM CM1 resist model can be used to determine resist loss by properly selecting the optical image plane for calibration. The model can then be used to identify toploss hotspots on a full chip and in some cases to correction of these patterns. In addition, the article will show how the model can be made more accurate by accounting for some 3D effects like diffusion through height.
Rigorous electromagnetic scattering simulation is used to characterize mask diffraction for fine structures of various types of EUVL masks. The Cr/SiO2 absorber mask, the etched multilayer mask and the new refilled multilayer mask are studied for lithography performance for line and space features for 32 nm node. The combined process window of 25 nm ISO line, 50 nm METAL1 line and 30 nm POLY line in a 90 nm pitch, are compared at s of 0.6. The biased Cr/SiO2 absorber masks have 182 nm DOF, while the biased etched binary mask has a higher DOF of 190 nm and the biased etched refilled binary mask has a DOF of 192 nm. The biased Cr/SiO2 absorber masks show twice of CD variation and process window degradation due to variations in sidewall profiles than the etched and refilled multilayer binary masks. The void defect in the reflection region of multilayer structures can be repaired via deposition of transparent materials instead of absorbing materials when patterning the refilled multilayer masks. Simulations show that target CD and process window can be fully restored when the depth and width of repairing materials deposited for repair is optimized.
Deprotection blur in EUV resists fundamentally limits the smallest sized dense features that can be patterned in a single exposure and development step. Several metrics have recently been developed to explore the ways that different resist and process parameters affect the deprotection blur in EUV resists. One of these metrics is based on the imaging fidelity of a sharp corner on a large feature. As this metric has involved the close inspection of printing fidelity of corner features, it has brought attention to an interesting phenomena: corners print differently whether or not the remaining resist edge contains 270 degrees of resist or 90 degrees of resist. Here we present experimental data across a wide sampling of leading resists to show this effect is real and reproducible. They provide aerial image modeling results assuming thin and realistic mask models that show no corner bias between the aerial images in the 90-degree and 270-degree configurations. They also compare modeled patterning results assuming several resist models including the single blur, dual blur, and Prolith models, none of which reproduce the corner biasing that is observed experimentally.
On the road to insertion of extreme ultraviolet (EUV) lithography into production at the 16 nm technology node and below, we are testing its integration into standard semiconductor process flows for 22 nm node devices. In this paper, we describe the patterning of two levels of a 22 nm node test chip using single-exposure EUV lithography; the other layers of the test chip were patterned using 193 nm immersion lithography. We designed a full-field EUV mask for contact and first interconnect levels using rule-based corrections to compensate for the EUV specific effects of mask shadowing and imaging system flare. The resulting mask and the 0.25-NA EUV scanner utilized for the EUV lithography steps were found to provide more than adequate patterning performance for the 22 nm node devices. The CD uniformity across the exposure field and through a lot of wafers was approximately 6.1% (3σ) and the measured overlay on a representative test chip wafer was 13.0 nm (x) and 12.2 nm (y). A trilayer resist process that provided ample process latitude and sufficient etch selectivity for pattern transfer was utilized to pattern the contact and first interconnect levels. The etch recipes provided good CD control, profiles and end-point discrimination. The patterned integration wafers have been processed through metal deposition and polish at the contact level and are now being patterned at the first interconnect level.
The fast rigorous model (FRM) is a first principles solver based on sequential simulations of photochemical reactions in photoresists. We report the evaluation of FRM relative to compact models (CM1) for NTD OPC model accuracy. We demonstrate equivalent or better accuracy to CM1 when FRM is combined with a CM1 model of the same composition. In the case of CTR to FRM comparison, FRM is 34% more accurate in calibration and prediction on average across 20 testcases. FRM is 5% more predictive than the most complex CM1 modelform tested with similar calibration accuracy. FRM supplemented with limited CM1 terms provides better verification accuracy for SRAF printing and hotspot detection. Further, the input data needed to train the FRM model in order to achieve high predictive accuracy is a fraction (1-5%) of that needed by more complex CM1 modelforms. Finally, we show through the Akaike Information Criteria method that FRM is more predictive than an equivalent CM1 model based on the degrees of freedom in the modelform and quantity of data available.
As increasing complexity of design and scaling continue to push lithographic imaging to its k1 limit, lithographers have been developing computational lithography solutions to extend 193nm immersion lithography to the 22nm technology node. In our paper, we investigate the beneficial source or mask solutions with respect to pattern fidelity and process variation (PV) band performances for 1D through pitch patterns, SRAM and Random Logic Standard Cells. The performances of two different computational lithography solutions, idealized un-constrained ILT mask and manhattanized mask rule constrain (MRC) compliant mask, are compared. Additionally performance benefits for process-window aware hybrid assist feature (AF) are gauged against traditional rule-based AF. The results of this study will demonstrate the lithographic performance contribution that can be obtained from these mask optimization techniques in addition to what source optimization can achieve.
Rigorous electromagnetic simulation with TEMPEST is used to provide benchmark data and understanding of key parameters in the design of topographical features of alignment marks. Periodic large silicon trenches are analyzed as a function of wavelength (530-800 nm), duty cycle, depth, slope and angle of incidence. The signals are well behaved except when the trench width becomes about 1 micrometers or smaller. Segmentation of the trenches to form 3D marks shows that a segmentation period of 2-5 wavelengths makes the diffraction in the (1,1) direction about 1/3 to 1/2 of that in the main first order (1,0). Transmission alignment marks nanoimprint lithography using the difference between the +1 and -1 reflected orders showed a sensitivity of the difference signal to misalignment of 0.7%/nm for rigorous simulation and 0.5%/nm for simple ray-tracing. The sensitivity to a slanted substrate indentation was 10 nm off-set per degree of tilt from horizontal.
