Jun Deng

Chongqing University

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Fang Tang

Chongqing University

Xin Lei

Chongqing University

Keliu Hu

China Electronics Technology Group Corporation

Zhou Shu

Nanjing Tech University

Xu Huang

Chongqing University

Lintao Liu

Northwest Institute For Non-Ferrous Metal Research

Deshu Zou

Beijing University of Technology

Guo Gao

Xi'an Institute of Optics and Precision Mechanics

Peng-Cheng Ji

Jiangsu University of Technology

Ming‐Chun Tang

Infineon Technologies (Germany)

Cooperative Institutions

Tsinghua University

Chongqing University

Chinese Academy of Sciences

University of Chinese Academy of Sciences

Beijing University of Technology

China Academy of Engineering Physics

Institute of Semiconductors

Southeast University

Zhejiang University

China Electronics Technology Group Corporation

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An Automatic Clock-Induced-Spurs Detector Based on Energy Detection for Direct Digital Frequency Synthesizer

Sensors (2022)

Xin Lei Junan Zhang Jun Deng Peng Yin Zhou Shu

A clock-induced-spurs detector, composed of a programmable low-pass filter (LPF), energy detector and spur detection algorithm, is presented and applied to a four-channel 1 gigabit-samples-per-second (GSPS) direct digital frequency synthesizer (DDS). The proposed detector realizes the detection of spurs based on energy-detection, and the spur detection algorithm is adopted to automatically extract the amplitude and phase of clock-induced spurs, generated by the intermodulation of harmonic spurs and multiple clocks. Finally, the extracted features are sent to auxiliary DDS to decrease the target spur, following which the detector can be turned off to save power. Additionally, the detected characteristics under different output conditions can be read out through the interface for rapid frequency switching. The proposed detector integrated into a DDS is fabricated with a 65 nm complementary metal oxide semiconductor (CMOS) process and has an area of 190 μm × 320 μm. The measured power consumption is roughly 38 mW, consuming 6% that of a single-channel DDS. The test results show that the spurious-free dynamic range (SFDR) of this DDS can be successfully enhanced from -43.1 dBc to roughly -59.9 dBc without any off-chip instruments. This effectively proves that the detection accuracy of this detector can reach around -81 dBm.

Spurious-free dynamic range

dBc

Direct digital synthesizer

Clock rate

10.3390/s22093396

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Citations (3)

Multi-scanning circuit for high-speed pulse sampling

Hedianzixue yu tance jishu (2006)

Jun Deng

It is pointed out that the key problem of high-speed pulse sampling is multi-sample readout. In this paper a multi-scanning circuit is introduced, including pass gate, multiplexer, logic control circuit and output amplifier. Circuit design and the components of circuit are given. Logic sequence of computer simulation shows that the scanning circuit is in normal working order, the amplified output can be sent to digital oscillograph or Virtual Instrument Studio LABVTEW for the redisplay of measured pulse waveforms.

Oscillograph

Sample and hold

Logic level

Control logic

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Study of System Modeling and Simulation Based on Mixed Domain for Analog-Digital Mixed SoC

Applied Mechanics and Materials (2013)

Jun Deng Liang Zhou Xiao Zong Huang Xu Huang Yu Jing Li

The design of digital-analog mixed SoC involves RF/analog and digital domains, how to effectively improve the design reliability and to reduce the development cycles has become a research hotspot. This paper establishes the appropriate behavioral models of RF / analog / digital IP modules, and carries out the behavioral simulation based on the built mixed-domain simulation platform and the behavioral libraries of RF/analog/digital IP module, which enhances the reliability and stability of mixed SoC design, and reduces the design cycle. Those explorations may be helpful to the designers of digital-analog mixed SoC.

Mixed-signal integrated circuit

Behavioral Modeling

10.4028/www.scientific.net/amm.423-426.2688

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Design and implementation of a mixed SoC for IF digital software radio receiver

Jun Deng Xu Huang Lintao Liu Yujing Li Xiaozong Huang

This paper presents a novel scheme for IF digital software radio receiver application, which integrates a high performance A/D converter and high-speed digital down converter (DDC) block into a SoC (system on chip) based on 32-bit RISC CPU. The proposed design can transform intermediate frequency (IF) analog signal to baseband digital signal and realize the real-time baseband signal processing. The simulation results indicate that The SFDR of ADC can achieve 88dB, and the SFDR of the DDC can reach to 70.59dBFS. The synthesized results of digital parts for the proposed SoC architecture on 0.18um CMOS technology reveals a maximum clock frequency of 116MHz and a total area of digital parts is 5.662mm ² , and the corresponding power consumption is below 150 mW. The ADC can reach to 250MSPS, whose power consumption is 263.6mW. The test results illuminates that the chip can work well. This design will have a good potential for wireless communication applications.

Spurious-free dynamic range

Radio receiver design

Digital down converter

Mixed-signal integrated circuit

Clock rate

10.1109/icaci.2013.6748513

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Design and Implementation of a Low-Power JESD204B Transmitter with Wideband Fractional-N Ring PLL in 40-Nm CMOS Process

Lecture notes in electrical engineering (2024)

Hao Chen Jun Deng Peng Fei Liao Shan-Shan Zhao Qiushi Wang

Wideband

PLL multibit

10.1007/978-981-97-2636-3_16

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A Survey on Trends of Image Compression Coding Standards

Jun Deng

The development process of Image compression coding standards has been introduced in brief.And the fundamental theories and involved technologies of several international standards for image compression are presented.Moreover,the realization of some important functions in these standards is also illustrated.At the end of this paper,the trends of image compression coding and some experience on it are also discussed and predicted.

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Citations (1)

Data flow anomaly detection technique and its application in Botnet detection

Information and Electronic Engineering (2011)

Jun Deng

Most of the current detection of P2P(Peer to Peer) Botnet adopts traditional reverse engineering method,which is very accurate,but difficult to be implemented and shows low efficiency.It becomes ineffective for variants.This paper attempts to find a data stream anomaly detection method suitable to the data stream application cases,and tries to apply it to P2P Zombie Virus detection.By monitoring network data stream,the special behaviors of P2P Zombie Virus in their spreading can be found.The locating of the zombie host can be realized by capturing those behaviors.

Zombie

Botnet

Anomaly (physics)

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Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

Journal of Semiconductors (2017)

Lintao Liu Yuhan Gao Jun Deng

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter , digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm 2 and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication.

Field-programmable analog array

Mixed-signal integrated circuit

Clock generator

Analog-to-digital converter

Digital-to-analog converter

Clock rate

10.1088/1674-4926/38/11/115001

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Citations (2)

Design of a SoC for Intermediate Frequency Digital Receiver

Lintao Liu Jun Deng

With the development of CMOS technology, the integration and miniaturization have become the trend of electronic devices.This paper proposes a scheme of system on chip (SoC) that realizes the monolithic integration of the intermediate frequency digital receiver based on CMOS technology, which integrates RF receiver front-end, A/D conversion, digital down conversion and baseband processing together.The chip is manufactured by 0.18um CMOS technology, and the area is 7x8mm 2 .The test of chip has completed within the RF reception signal range of 0.5~4GHz, The system noise of RF receiving module is below 10dB, the image rejection is greater than 40dB, the SFDR of ADC can reach to 80.22 dB, and the maximum operating frequency of DDC and CPU can arrive up to 100MHz.the test results can meet the requirements of the project evaluation index.The chip has great potential applications in the miniaturization, integration and high reliability of the electronic systems.

10.2991/icmit-16.2016.39

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Key technology of visible command system for mine rescue

Coal science and technology (2007)

Jun Deng Yongfei Jin Shugang Li Wen Hu Jianping Wang

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