Chung‐Yi Li

Chang Gung University

Author Statistics

Papers

Citation

H-Index

i-10 index

Research Trends

Author Order

Document Type

Co-Authors

Yuan‐Ho Chen

Chang Gung University

Tsin‐Yuan Chang

National Tsing Hua University

Kuo‐Sheng Chin

Chang Gung University

Lu‐An Lai

Chang Gung University

Chia-yuan Chou

National Tsing Hua University

Huayan Jin

Hangzhou Dianzi University

Hwai-Pwu Chou

National Tsing Hua University

An-Chien Li

Chang Gung University

Kuo–Feng Hsu

National Defense Medical Center

Chin Hsia

Chang Gung University

Cooperative Institutions

Chang Gung University

National Tsing Hua University

National Yang Ming Chiao Tung University

National Taiwan University

Tri-Service General Hospital

Chang Gung Memorial Hospital

National Defense Medical Center

Linkou Chang Gung Memorial Hospital

National Central University

University of California, San Diego

Author Statistics

Papers

Citation

H-Index

i-10 index

Research Field

Low‐latency and power‐efficient row‐based binary‐weighted compensator for fixed‐width Booth multiplier

International Journal of Circuit Theory and Applications (2024)

Chung‐Yi Li Hong‐Chi Hu Yuan‐Ho Chen Shinn‐Yn Lin

Abstract Fixed‐width Booth multiplier (FWBM) plays a significant role in the arouse of approximate computing (AC) field. In this paper, a row‐based binary‐weighted compensator (RBC) for fixed‐width Booth multiplication is proposed. The derived binary‐weighted close‐form minimizes the conversion loss and hardware cost. With the proposed close‐form, the partial product array can be reduced dramatically. Consequently, the compact FWBM with the proposed RBC not only shortens the critical path to at least 24 % but also minimizes the power dissipation to at least 44%. Moreover, the proposed RBC outperforms the state‐of‐art with a maximum merit improvement of 39%. By implementing the proposed RBC‐FWBM in the FIR filter, we manage to demonstrate the practicality of the proposed design with a significant reduction in power‐dissipation and delay while maintaining high accuracy.

Booth's multiplication algorithm

Power–delay product

Power of two

10.1002/cta.4207

Cite

Citations (0)

High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree

IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2010)

Yuan‐Ho Chen Tsin‐Yuan Chang Chung‐Yi Li

In this brief, by operating the shifting and addition in parallel, an error-compensated adder-tree (ECAT) is proposed to deal with the truncation errors and to achieve low-error and high-throughput discrete cosine transform (DCT) design. Instead of the 12 bits used in previous works, 9-bit distributed arithmetic-precision is chosen for this work so as to meet peak-signal-to-noise-ratio (PSNR) requirements. Thus, an area-efficient DCT core is implemented to achieve 1 Gpels/s throughput rate with gate counts of 22.2 K for the PSNR requirements outlined in the previous works.

Tree (set theory)

10.1109/tvlsi.2009.2037968

Cite

Citations (42)

Bandwidth and gain enhancement of LTCC 60-GHz patch antenna by using AMC structure

Journal of Electromagnetic Waves and Applications (2019)

Hua‐Juan Lee Eric S. Li Chung‐Yi Li Yu-You Lin Roger Y. Lu

This study presents 60-GHz patch antennas backed by artificial magnetic conductor (AMC) arrays for bandwidth and gain enhancement. Low-temperature cofired ceramic technology was adopted for antenna fabrication. Three patch antennas implemented with different AMC configurations were simulated and compared. The patch-shaped AMC was selected for final antenna fabrication because of its superior performance. The proposed antenna provided a measured impedance bandwidth of 50.2 − 68 GHz or an equivalent fractional bandwidth of 30.3%. The measured maximum gain was 7.8 dBi at 63 GHz.

Patch antenna

High-gain antenna

10.1080/09205071.2019.1614483

Cite

Citations (4)

Compact T-complementary split-ring resonator antenna and antenna array

Journal of Electromagnetic Waves and Applications (2021)

Huayan Jin Chi-Yang Chiou An-Chien Li Chung‐Yi Li Kuo‐Sheng Chin

A compact T-complementary split-ring resonator (CSRR) antenna was developed. Different from traditional designs, the proposed CSRR functioned not only as a loading structure but also as a radiator. The operation of the T-CSRR antenna was similar to that of a slot antenna with a gain of 3.1 dBi. Because of the loading effect of the CSRR, the size of the radiator of the proposed antenna was only 0.14λ0 × 0.26λ0. The circuit sizes of the proposed T-CSRR antenna were 50% and 74% smaller than those of the traditional half-wavelength slot and T-shaped monopole antennas, respectively. For further gain enhancement, the performance of two feasible array arrangements, namely collinear and parallel arrays with 1 × 4 T-CSRR elements, were compared, which revealed that the parallel 1 × 4 T-CSRR antenna array can achieve a gain of 9 dBi at 2.45 GHz.

Split-ring resonator

Radiator (engine cooling)

10.1080/09205071.2021.1934903

Cite

Citations (2)

Pattern‐reconfigurable dual‐band dipole antenna array with four switchable beams for full coverage in horizontal plane

IET Microwaves Antennas & Propagation (2020)

Changwei Su Huayan Jin Chung‐Yi Li Yi‐Jyun Liao Kuo‐Sheng Chin

In this study, we develop a pattern-reconfigurable dual-band 1 × 2 dipole antenna array for operation in 2.45- and 5.5-GHz bands. Parasitic directors are added to the antenna to change the shape of the radiation pattern, and the length of parasitic directors are adjusted using diode switches; therefore, each band can switch four beams in 0° (front broadside), 90° (right endfire), 180° (back broadside), and 270° (left endfire) directions to achieve full coverage in the horizontal plane. For demonstration, one prototype of the proposed pattern-reconfigurable dual-band dipole antenna array was fabricated and measured. Measured results indicated that dual-band operation was achieved with the maximum impedance bandwidths of 30.8% and 46% in 2.45- and 5.5-GHz bands, respectively. Four switchable beams were obtained with a maximum gain of 5.3 dBi and a front-to-back ratio up to 17.3 dB.

Broadside

Multi-band device

Reconfigurable antenna

Horizontal plane

10.1049/mia2.12020

Cite

Citations (1)

A Self-Referred Clock Jitter Measurement Circuit in Wide Frequency Range

Asian Test Symposium (2006)

Chung‐Yi Li Chia-yuan Chou Tsin‐Yuan Chang

In this paper, a jitter measurement circuit with its calibration scheme for measuring peak-to-peak jitters of clock is proposed and demonstrated. By applying the Vernier oscillators, the mismatching effect and area overhead are both reduced compared with conventional circuits using Vernier delay lines. With high resolution (7.98ps) and high speed (20.08ps/5k samples), the proposed circuit develops a tunable frequency range of input clock and improves the accuracy of the measurement results. The proposed circuit may be applied in multi-clocks' measurement

10.1109/ats.2006.15

Cite

Citations (0)

Fast locking adaptive PLL using Dual-Edge Phase-Frequency Detector

Microelectronics Journal (2015)

Chung‐Yi Li

Three-stage PLL with a Dual-Edge Phase-frequency Detector (DE-PFD) is proposed to reduce the locking time and to reduce jitter when locked. The DE-PFD speeds up the locking time by detecting the phase difference between the reference clock signal and the PLL׳s feedback signal of the divider circuit in both the rising edge and the falling edge. Meanwhile, the control signal generated from the DE-PFD can switch the loop bandwidth automatically. The locking status detection using DE-PFD saves the hardware overhead and switches the bandwidth smoothly. The DE-PFD is switched to the single-edge PFD to decrease the jitter further when the PLL is locked. The implemented proposed three-stage 1.6 GHz PLL under the TSMC 0.18 μm CMOS process shows the pre-simulation result of 56% locking time improvement as compared to the conventional PLL and the measured results of the RMS jitter reduced from 13.36 to 11 ps and the peak-to-peak jitter from 60 ps to 44 ps. When the bandwidth switching mechanism is activated, the power level of interference is reduced by 10 dBm.

PLL multibit

Signal edge

Phase frequency detector

10.1016/j.mejo.2015.08.012

Cite

Citations (8)

Simple and hardware‐efficient row‐based direct‐mapping estimators in fixed‐width modified Booth multipliers

International Journal of Circuit Theory and Applications (2021)

Chung‐Yi Li Yuan‐Ho Chen Lu‐An Lai Wen‐Chi Ye Jun Yang

Summary The great demand of high‐performance fixed‐width two's‐complement modified Booth multipliers (FWBM) arises because of the wide applications of approximate computing. In this paper, a row‐based direct‐mapping (RDM) method for designing error estimators in FWBM is proposed. The proposed closed form is derived from probability summation of each entire row to avoid the long setup time of exhaustive simulations. Consequently, a simple and systematic procedure by the Karnaugh map can be utilized to design low‐error and hardware‐efficient compensation circuits for various widths of FWBMs. By checking the leading column of the truncation part, the extendable design principle can be easily applied to different lengths and different columns inspected. We use Synopsys Design Compiler and TSMC 90 nm standard cell library to synthesize the register transfer language (RTL) design of our proposed estimators. In addition, the RDM is synthesized using the Xilinx Vivado tool with Xilinx Kintex‐7 XC7K325T‐2FFG900C FPGA. Results of software simulation, hardware synthesis, and implementation experiment validate the high accuracy, hardware saving, and power efficiency of the proposed RDM estimators.

RDM

Standard cell

High-Level Synthesis

10.1002/cta.2937

Cite

Citations (2)

A Fast Locking-in and Low Jitter PLLWith a Process-Immune Locking-in Monitor

IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2013)

Chung‐Yi Li Chung-Len Lee Ming-Hong Hu Hwai-Pwu Chou

In this brief, a digital-control adaptive phase-locked loop (PLL) with a digital locking-in monitor (LIM) consisting of a time-to-digital converter (TDC) and a bandwidth control unit (BCU) is proposed to reduce the locking time as well as to suppress the jitter when locked. It uses a delay-independent threshold in a dual-slope transfer function to detect the locked state according to the counting result of the proposed TDC, which feeds to the BCU to switch the bandwidth of PLL. Then the PLL is switched from a wide loop bandwidth (6 MHz) to a narrow bandwidth (3 MHz) in the locked state. To verify the proposed scheme, the proposed adaptive PLL is implemented in a TSMC 0.18 μm 1P6M CMOS process with a supply voltage of 1.8 V. The measurement results show that the locking time is reduced by 67% while with a RMS jitter of only 8.79 ps when operating at 1.6 GHz.

PLL multibit

10.1109/tvlsi.2013.2285977

Cite

Citations (10)

Zeroing of power supply noise sensitivity for ring oscillators operating from 1 to 4 GHz

Microelectronics Journal (2017)

Chung‐Yi Li Bo-Xun Wu

A zeroing design for both positive and negative power supply noise sensitivities of the VCO to alleviate the jitter caused by the supply noise for the PLL operating over a range of 1–4 GHz is proposed and demonstrated. The design uses a polarity check module to check the noise sensitivity polarity (positive or negative) of the supply noise. Then it uses a modified delay cell for which both its VDS and VGS can be adjusted to gain the bipolarity compensation. In addition, the calibration can be activated automatically when the PLL is locked or when the operating frequency is changed.

Polarity (international relations)

Ring oscillator

10.1016/j.mejo.2017.08.001

Cite

Citations (1)