The variation in electric conductivity was examined for laser irradiation with various beam intensities. A 532-nm continuous wave laser was irradiated onto inkjet-printed silver lines on a glass substrate and the electrical resistance was measured in situ during the irradiation. The results demonstrate that electrical conductivity varies nonlinearly with laser intensity, and has a minimum specific resistance of 3.1 x 10(-8) Ωm at 4 kW/cm2 irradiation. These results are interesting because the specific resistance achieved by the present laser irradiation was approximately 1.9 times lower than the best value obtainable by oven heating, even though it was still higher by 1.9 times than that of bulk silver. It is also demonstrated that the irradiation time required to complete the sintering process decreases with laser intensity. The numerical simulation of laser heating shows that the heating temperature could be as high as 250 degrees C for laser sintering, while it is limited to 250 degrees C for oven sintering. The characteristics of sintering with laser intensity based on the results of field emission scanning electron microscope images are discussed.
In this paper, a non-magnetic circulator, which realizes non-reciprocal signal flows by sequentially switching delay lines, is presented in 28-nm fully depleted silicon-on-insulator (FDSOI) CMOS process. The proposed circulator is designed differentially to increase power handling capability and bandwidth. The bandwidth of insertion loss and isolation can be extended by latticely coupled inductors used in the differential synthetic delay lines. The characteristic impedance of the delay lines is determined by considering the channel resistance of CMOS transistor. The measured insertion losses of transmitter (TX) to antenna (ANT) and ANT to receiver (RX) are 2.5 dB and 2.6 dB, respectively. TX to RX isolation is $> 20\ \text{dB}$ up to 7 GHz. The measured TX input power 1 dB compression point is 4.7 dBm at 3.5 GHz. The chip size of the differential circulator is $1.33\times 0.72\ \text{mm}^{2}$ , which is as small as a single ended version, thanks to the coupled inductors.
This article presents a compact Ka-band bi-directional power amplifier-low-noise amplifier (PA-LNA) utilizing a three-stack power amplifier (PA) in a 28-nm CMOS process. In the proposed PA-LNA, the input and output of the three-stack PA are cross-coupled with the output and input of the common-source (CS) low-noise amplifier (LNA). This configuration neutralizes the gate-drain capacitance of the LNA through the parasitic capacitance ( $C_{\text{para}.}$ ) of the three-stack PA, improving stability and gain in the LNA mode. Simultaneously, the three-stack PA achieves higher output power and gain in the PA mode. Moreover, since $C_{\text{para}.}$ of the transistors are connected in series, the transistor sizes for the PA and LNA can be selected asymmetrically, alleviating the tradeoff between linearity in the PA mode and dc power consumption in the LNA mode. Additionally, the output conductance of the off-state PA is enhanced by stacking more transistors and applying appropriate biasing to keep them in the off-state, leading to an improved noise figure (NF) in the LNA mode. Furthermore, transformer-based switching matching networks (MNs) enable fully bi-directional operation within a compact die area of 0.1 mm $^2$ . In the PA mode, the proposed PA-LNA achieves a peak gain of 20.4 dB with a 3-dB bandwidth of 8.1 GHz (27.3–35.4 GHz), a saturated output power ( $P_{\text{sat}}$ ) of 17.4 dBm, a peak power-added-efficiency (PAE) of 17.2%, and an error vector magnitude (EVM) of $-$ 32.0 dB with 256-quadrature amplitude modulation (QAM) at an 800-MBaud symbol rate and 7.6-dBm average output power. In the LNA mode, the proposed PA-LNA achieves a peak gain of 17.3 dB with a 3-dB bandwidth of 8 GHz (28.0–36.0 GHz), a noise figure (NF) of 5.3 dB, and an input third-order intercept point (IIP3) of 0 dBm.
A threshold voltage compensation pixel circuit was developed for active-matrix organic light emitting diodes (AMOLEDs) using amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO-TFTs). Oxide TFTs are n-channel TFTs; therefore, we developed a circuit for the n-channel TFT characteristics. The proposed pixel circuit was verified and proved by circuit analysis and circuit simulations. The proposed circuit was able to compensate for the threshold voltage variations of the drive TFT in AMOLEDs. The error rate of the OLED current for a threshold voltage change of 3 V was as low as 1.5%.
A three-bit flash analog-to-digital converter (ADC) consisting of inverter-based comparators and logic gates using amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs) was developed. The TFT has a bottom gate structure with a methyl-siloxane-based organic spin-on-glass passivation layer, which reduces the plasma damage on the active layer. A bootstrapped logic gate structure was used in the proposed ADC to overcome the reduced output swing in the inverters and the NAND gates caused by using only n-type a-IGZO TFTs. The output signals of the developed three-bit flash ADC with a-IGZO TFTs well matched the analog inputs. The output voltage swing was 0.2–3.6 V, well matching the simulation result. The three-bit flash ADC was verified up to the 1 kHz operation frequency, and thus can be used in sensor applications such as the wearable sensor display and the integrated biosensing platform.
This article presents a nonmagnetic circulator that realizes nonreciprocity by sequentially switching delay lines, which is fabricated in a 28-nm fully depleted silicon-on-insulator (FDSOI) CMOS process. The electrical length of delay lines is 90 $^{\circ}$ at the switching clock frequency of 1.65 GHz. The proposed circulator is designed differentially to increase the bandwidth as well as power-handling capability. The differential synthetic delay lines can utilize latticely coupled inductors with an optimized winding sequence, resulting in an ultra-wideband. The characteristic impedance of the delay lines is determined by considering the channel resistance of CMOS transistor for a higher isolation. The measured insertion losses of the transmitter (TX) to the antenna (ANT) and ANT to the receiver (RX) are 2.5 and 2.6 dB, respectively. The TX to RX isolation is $>$ 20 dB up to 7 GHz. The circulator demonstrates a TX input power 1-dB compression point (IP1 dB) of 4.7 dBm and ANT input third-order intercept point (IIP3) of 17.2 dBm at 3.5 GHz with 1.65-GHz clock. The achieved highest data rate is 9.8 Gb/s using 128 quadrature amplitude modulation (QAM) with an error vector magnitude (EVM) of 3.9% at a carrier frequency of 2.475 GHz. The measured noise figure (NF) is consistent with the ANT to RX path insertion loss except for the harmonics of the clock frequency. Only the quadrature clock generation circuitry consumes a dc power of 20 mW. The circulator occupies 0.96 mm $^{2}$ , which is comparable to a single-ended version because of the differentially coupled inductors.
This paper demonstrates a 26.5-GHz 2-D Butler matrix based 4×2 array switched beamformer. By using a 2-D Butler matrix, feed lines between IC and antennas are uniform, which is a critical problem in an integrated Butler matrix for a 1- D array since it requires complex phase matched routing on PCB. A proposed switched beamformer consists of a signal distribution IC and two switched beamformer ICs. Reconfigurable switches with a function of power divider/combiner are integrated for additional beam patterns. The proposed switched beamformer can generate total 22 beams, which cover a whole scan angle with a low gain variation. Measured beam patterns show that the proposed switched beamformer can cover any 3-D spatial angle of ±44° in azimuth and ±43° in elevation even with a low spatial beam resolution. To our knowledge, this is the first 2-D array switched beamformer based on the Butler matrix in millimeter wave bands.
This paper presents a new design for an active quasi-circulator that utilizes a phase alternated differential amplifier to achieve ultra-wideband and compact size in a 28-nm CMOS process. The proposed active quasi-circulator is based on a differential two-stage distributed amplifier, where the differential outputs of the phase alternated amplifier in second stage are cross-connected to the differential outputs of the amplifier in first stage. The use of the phase alternated differential amplifier allows for wideband isolation regardless of frequency. Furthermore, interstage inductor, which is located between two transistors of amplifier makes the circulator more wideband by maintaining frequency response of two transmission lines identically. The measured transmitter (TX) to receiver (RX) isolation is >21 dB, -3 dB bandwidth of TX to antenna (ANT) is from 20 to 38.5 GHz with 4.5 dB of peak gain at 29.8 GHz, minimum insertion loss of ANT to RX is 4.3 dB. The measured TX to ANT output power 1 dB compression point is 7.3 dBm at 28 GHz with DC power consumption of 107 mW. The circulator occupies only 0.07 mm 2 , thanks to coupled inductors which contribute to compact size.
Amorphous silicon thin film transistors (TFTs) have been used widely due to good uniformity and low process cost. However, They are not suitable for a circuit due to the low carrier mobility. Amorphous Indium-Gallium-Zinc-Oxide Thin Film Transistor (a-IGZO TFT) exhibits higher mobility and lower leakage current than amorphous silicon TFT and it is common to use only n-type a-IGZO TFT due to a poor electrical property of p-type TFT. In this paper, we developed operational amplifier (op-amp) circuit using only the n-type a-IGZO TFTs. Recently, medical device circuits for measuring bio-signals are being implemented on a wearable devices. Oxide TFTs are suitable for the integrated circuit for such applications. The analog signal processing such as amplification, and filtering of much noise are necessary for analog electrical signals introduced from bio-sensors. The op-amp is most widely used amplifiers due to ideal linear performance characteristics. An op-amp is composed of two input voltages (+V in , -V in ), two power supply voltages (+V DD , -V DD ) and one output voltage (Vout). It amplifies the voltage difference between the two input voltages of the non-inverting and inverting inputs (+V in , -V in ). The op-amp with a-IGZO TFTs has lower gain than that of the op-amp by CMOS process and need increase of the gain by cascaded amplifier stages. We developed a single power supply (+V DD = +15V) OP amp with improved gain. The circuit is composed of three stages: the first is differential amplifier(T1~T8) of input stage, the second is common-source amplifier(T9~T17), and the third is output buffer(T18~T19) of the output stage. The differential amplifier of the first stage amplified the differential voltage for given input signals (+V in , -V in ). The output voltage was amplified at the common-source amplifier stage of the second stage. Common-source amplifiers were used for a large voltage gain. After optimization of the circuits, the input voltage of 0.05V was amplified to about 13V.
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