In recent years, the operation speed of SAR ADCs has improved with the scaling of CMOS technology. SAR ADCs achieve a few hundreds of MS/s with 8-to-10b resolution. The SNR of high-speed SAR ADCs is mainly dominated by comparator noise and usually limited to 50 to 60dB. The power consumption increases exponentially to suppress comparator noise in a limited comparison time to improve SNR. Noise-tolerant SAR ADCs [1] reduce comparator power in the first few bit cycles by using a coarse comparator. However, the fine comparator in the remaining bit cycles still consumes significant power to achieve an SNR greater than 60dB. SAR-assisted pipelined ADCs [2,3] do not require a low-noise comparator, but design restrictions in advanced CMOS processes make high-performance amplifier design challenging. Using a low-gain or a dynamic amplifier induces gain errors between stages. Besides, the amplifier and back-end stages result in extra noise and area. Digital-slope ADCs [4] are inherently low-noise by quantizing the signal in the time domain, but the hardware cost grows exponentially with resolution and the maximum conversion rate is halved with each additional bit of resolution. Hence this ADC type is unattractive for resolutions higher than 8b. This paper reports a 12b hybrid ADC combining a 7b low-power SAR coarse ADC with a 6b low-noise digital-slope fine ADC. The 100MS/s ADC achieves 64.43dB SNDR at Nyquist input with 0.35mW from a 0.9V supply.
Digital wireless communication applications such as UWB and WPAN necessitate low-power high-speed ADCs to convert RF/IF signals into digital form for subsequent baseband processing. Considering latency and conversion speed, flash ADCs are often the most preferred option. Generally, flash ADCs suffer from high power consumption and large area overhead. On the contrary, SAR ADCs have low power dissipation and occupy a small area. However, a SAR ADC needs several comparison cycles to complete one conversion, which limits its conversion speed. The highest single-channel operation speed of previously reported SAR ADCs is 625MS/s [1]. The ADC in [1] utilizes a 2b/step structure. For non-multi-bit/step SAR ADCs, the highest reported conversion rate is 300MS/s [2]. The structure of a comparator-based binary-search ADC is between that of flash and SAR ADCs [3]. Compared to a flash ADC (high speed, high power) and a SAR ADC (low speed, low power), a binary-search ADC achieves balance between operation speed and power consumption. This paper reports a 5b asynchronous binary-search ADC with reference-range prediction. The maximum conversion speed of this ADC is 800MS/s at a cost of 2mW power consumption.
This paper reports a subranged SAR ADC consisting of a 3.5-bit flash coarse ADC, a 6-bit SAR fine ADC, and a differential segmented capacitive DAC. The flash ADC controls thermometer MSBs of the DAC and SAR ADC controls the binary LSBs. The segmented DAC improves DNL during MSB transitions. The merged switching of MSB capacitors enhances operation speed. The 9-bit 150-MS/s ADC consumes 1.53 mW from a 1.2-V supply. The ENOB is 8.69 bit and ERBW is 100 MHz. The FOMs at 1.2 V, 150 MS/s and 1 V, 100 MS/s are 24.7 and 17.7 fJ/conversion-step, respectively. At 1.3-V supply voltage, the sampling rate achieves 200 MS/s.
This paper presents an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) for biomedical applications. To reduce energy consumption, a bypass window technique is used to select switching sequences to skip several conversion steps when the signal is within a predefined small window. The power consumptions of the capacitive digital-to-analog converter (DAC), latch comparator, and digital control circuit of the proposed ADC are lower than those of a conventional SAR ADC. The proposed bypass window tolerates the DAC settling error and comparator voltage offset in the first four phases and suppresses the peak DNL and INL values. A proof-of-concept prototype was fabricated in 0.18-μm 1P6M CMOS technology. At a 0.6-V supply voltage and a 200-kS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio of 57.97 dB and consumes 1.04 μW, resulting in a figure of merit of 8.03 fJ/conversion-step. The ADC core occupies an active area of only 0.082 mm 2 .
The successive approximation register (SAR) ADC is the most energy efficient architecture with moderate conversion rate and resolution. However, its comparator noise limits its resolution without sacrificing power efficiency. The delta-sigma modulator (DSM) is the most popular architecture for achieving high SNDR due to its oversampling, but the bulky operational amplifier (op-amp) makes it area inefficient. In LTE Advanced, the bandwidth (BW) of downlink ADCs needs to be configured according to the number of inter-band non-contiguous carrier aggregation (NCCA), which motivates us to combine the benefits of both architectures to reduce area and power consumption simultaneously with high SNDR. The noise-shaping SAR ADC [1] suppresses the comparison and quantization noise in signal BW using a simple cascaded FIR-IIR filter, which obviates the need for a power-hungry low-noise comparator or high-performance op-amp. To some extent, the noise-shaping SAR ADC is a hybrid of DSM and SAR ADCs. Hence, it has the potential to achieve the high resolution and good power efficiency of DSM and SAR ADCs, respectively. However, the passive sampling in an FIR filter introduces considerable thermal noise to the ADC, making it difficult to achieve a high SNR. This work presents an energy-efficient noise-shaping SAR ADC that uses a gain-enhanced dynamic amplifier and some capacitors to construct a low-noise dynamic FIR-IIR filter. The prototype achieves a peak SNDR of 79.74dB over a 5MHz BW with a power consumption of 0.46mW from a 1V supply.
The cost of horizontal drilling and hydraulic fracturing in shale oil and gas development is very high. In order to improve economic benefits, it is necessary to carry out the research on sweet spot discrimination immediately. This paper first analyzed the main factors of sweet spot in North American shale which contained total organic carbon content, rock brittleness, porosity and fracture. Then it was clear that rock physics analysis was the key of sweet spot discrimination, while the quantitative logging interpretation of reservoir parameter is the basis of rock physics. For the logging quantitative evaluation problem in North American shale, a kerogen-corrected logging model has been used, and the core technology and flowchart of reservoir quantitative evaluation based on elemental capture spectroscopy logging have been built in shale. On the basis of logging interpretation result, rock physics analysis has been carried out, and the results showed that the porosity was the key factor of affecting production in block A. Because P-wave impedance can characterize porosity effectively, the technology combination of pre-stack inversion and fracture analysis has been used to predict sweet spot of shale in block A. The result was used to guide drilling deployment and fracture optimization design. And the shale oil and gas production has increased greatly. The total organic carbon content and rock brittleness are the key factors of affecting shale oil and gas production in block B. So pre-stack simultaneous inversion technique was used to solve the problem of sweet spot discrimination in block B. Drilling results confirmed that the production in sweet spot region was very high.
This paper presents a new subrange analog-to-digital converter (ADC): a binary-search coarse ADC + a SAR fine ADC. The binary-search ADC improves conversion speed and gives coarse capacitors longer settling time. This ADC uses an RC hybrid DAC to reduce the unit capacitor count by 2. The rotation function of coarse capacitors enhances capacitor array linearity. The prototype in 90-nm CMOS only occupies an active area of 0.06 mm 2 . From a 0.9-V supply, the power consumption is 0.32 and 0.58 mW at 10 and 25 MS/s, respectively. At 10 MS/s, the peak ENOB is 10.2 bit. At 25 MS/s, the peak ENOB is 9.9 bit and FOM is 29 fJ/conversion-step.
This paper reports a successive-approximation analog-to-digital converter (ADC) which combines the bypass window and direct switching technique to tolerate the incomplete settling error and reduce the control logic delay. A small unit capacitor cell reduces the power consumption and settling time. The 10-bit prototype is fabricated in a 40nm CMOS process. At 200 MS/s and 0.9-V supply, this ADC consumes 0.82 mW and achieves an SNDR of 57.16 dB, resulting in an FOM of 13.9 fJ/Conversion-step.
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