Tan Nguyen

Lawrence Berkeley National Laboratory

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Ann Almgren

Lawrence Berkeley National Laboratory

Weiqun Zhang

Lawrence Berkeley National Laboratory

John Shalf

Lawrence Berkeley National Laboratory

Didem Unat

Koç University

Samuel Williams

Lawrence Berkeley National Laboratory

Muhammad Nufail Farooqi

Leibniz Supercomputing Centre

Scott B. Baden

Lawrence Berkeley National Laboratory

Swathi Gurumani

Advanced Digital Sciences Center

Kyle Rupnow

Advanced Digital Sciences Center

Yao Chen

Hubei University of Technology

Cooperative Institutions

Lawrence Berkeley National Laboratory

National Energy Research Scientific Computing Center

University of California, Berkeley

University of California, San Diego

University of Illinois Urbana-Champaign

Pacific Northwest National Laboratory

Sandia National Laboratories California

University of California System

Lawrence Livermore National Laboratory

University of Chicago

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AMReX-Codes/amrex: AMReX 19.05.1

Ann Almgren Vince Beckner Johannes Blaschke Cy Chan Marc Day

10.5281/zenodo.2754709

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Citations (2)

The Performance and Energy Efficiency Potential of FPGAs in Scientific Computing

Tan Nguyen Samuel Williams Marco Siracusa Colin MacLean Douglas W. Doerfler

Hardware specialization is a promising direction for the future of digital computing. Reconfigurable technologies enable hardware specialization with modest non-recurring engineering cost. In this paper, we use FPGAs to evaluate the benefits of building specialized hardware for numerical kernels found in scientific applications. In order to properly evaluate performance, we not only compare Intel Arria 10 and Xilinx U280 performance against Intel Xeon, Intel Xeon Phi, and NVIDIA V100 GPUs, but we also extend the Empirical Roofline Toolkit (ERT) to FPGAs in order to assess our results in terms of the Roofline Model. Although FPGA performance is known to be far less than that of a GPU, we also benchmark the energy efficiency of each platform for the scientific kernels comparing to microbenchmark and technological limits. Results show that while FPGAs struggle to compete in absolute terms with GPUs on memory- and compute-intensive kernels, they require far less power and can deliver nearly the same energy efficiency.

Xeon

Benchmark (surveying)

Reconfigurable Computing

Xeon Phi

10.1109/pmbs51919.2020.00007

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Citations (25)

Devastator: A Scalable Parallel Discrete Event Simulation Framework for Modern C++

John Bachan Jianlan Ye Xuan Jiang Tan Nguyen Mahesh Natarajan

Discrete-Event Simulation

10.1145/3615979.3656061

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Citations (1)

FPGA‐based HPC accelerators: An evaluation on performance and energy efficiency

Concurrency and Computation Practice and Experience (2021)

Tan Nguyen Colin MacLean Marco Siracusa Douglas W. Doerfler Nicholas J. Wright

Abstract Hardware specialization is a promising direction for the future of digital computing. Reconfigurable technologies enable hardware specialization with modest non‐recurring engineering cost, but their performance and energy efficiency compared to state‐of‐the‐art processor architectures remain an open question. In this article, we use FPGAs to evaluate the benefits of building specialized hardware for numerical kernels found in scientific applications. In order to properly evaluate performance, we not only compare Intel Arria 10 and Xilinx U280 performance against Intel Xeon, Intel Xeon Phi, and NVIDIA V100 GPUs, but we also extend the Empirical Roofline Toolkit (ERT) to FPGAs in order to assess our results in terms of the Roofline model. We show design optimization and tuning techniques for peak FPGA performance at reasonable hardware usage and power consumption. As FPGA peak performance is known to be far less than that of a GPU, we also benchmark the energy efficiency of each platform for the scientific kernels comparing against microbenchmark and technological limits. Results show that while FPGAs struggle to compete in absolute terms with GPUs on memory‐ and compute‐intensive kernels, they require far less power and can deliver nearly the same energy efficiency.

Xeon

Benchmark (surveying)

Xeon Phi

Reconfigurable Computing

10.1002/cpe.6570

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Citations (20)

Perilla: metadata-based optimizations of an asynchronous runtime for adaptive mesh refinement

IEEE International Conference on High Performance Computing, Data, and Analytics (2016)

Tan Nguyen Didem Unat Weiqun Zhang Ann Almgren Muhammad Nufail Farooqi

Hardware architecture is increasingly complex, urging the development of asynchronous runtime systems with advance resource and locality management supports. However, these supports may come at the cost of complicating the user interface while programming remains one of the major constraints to wide adoption of asynchronous runtimes in practice. In this paper, we propose a solution that leverages application metadata to enable challenging optimizations as well as to facilitate the task of transforming legacy code to an asynchronous representation. We develop Perilla, a task graph-based runtime system that requires only modest programming effort. Perilla utilizes metadata of an AMR software framework to enable various optimizations at the communication layer without complicating its API. Experimental results with different applications on up to 24K processor cores show that Perilla can realize up to 1.44x speedup over the synchronous code variant. The metadata enabled optimizations account for 25% to 100% of the performance improvement.

Speedup

10.5555/3014904.3015013

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Citations (5)

BoxLib with Tiling: An Adaptive Mesh Refinement Software Framework

SIAM Journal on Scientific Computing (2016)

Weiqun Zhang Ann Almgren Marc Day Tan Nguyen John Shalf

In this paper we introduce a block-structured adaptive mesh refinement software framework that incorporates tiling, a well-known loop transformation. Because the multiscale, multiphysics codes built in BoxLib are designed to solve complex systems at high resolution, performance on current and next generation architectures is essential. With the expectation of many more cores per node on next generation architectures, the ability to effectively utilize threads within a node is essential, and the current model for parallelization will not be sufficient. We describe a new version of BoxLib in which the tiling constructs are embedded so that BoxLib-based applications can easily realize expected performance gains without extra effort on the part of the application developer. We also discuss a path forward to enable future versions of BoxLib to take advantage of NUMA-aware optimizations using the TiDA portable library.

Adaptive Mesh Refinement

10.1137/15m102616x

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Citations (46)

Benefits of Optimistic Parallel Discrete Event Simulation for Network-on-Chip Simulation

Maximilian Bremer Nirmalendu Patra Tan Nguyen Dilip Vasudevan Cy Chan

The end of Moore's law has placed a two-fold demand on hardware simulation. Firstly, efficient co-design requires fast simulation of hardware systems in order to vet proposed designs. Secondly, modern simulator platforms need to become increasingly concurrent as well. To address these challenges, we develop an optimistic time warp-based parallelization for the Structural Simulation Toolkit (SST). Our optimistic PDES engine hides synchronization costs by speculatively executing tasks, leading to better compute resource utilization on modern multicore architectures. Given the significant engineering effort to make custom existing hardware models reversible, we also develop a new SST component, called escher. The escher workflow instruments arbitrary SST applications and replays event traces through the different SST parallelizations. This is a useful tool for hardware engineers who want to understand the benefits of optimistic parallelization before undertaking the significant software engineering effort to make their hardware models reversible. We demonstrate this workflow by generating traces for a tiled mesh-NOC architecture and show a 2.1x to 3.7x speed-up using our optimistic SST parallelization versus the current conservative SST parallelization.

Discrete-Event Simulation

Multi-core processor

Component (thermodynamics)

Execution model

10.1109/ds-rt58998.2023.00013

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Citations (0)

A software-based dynamic-warp scheduling approach for load-balancing the Viola–Jones face detection algorithm on GPUs

Journal of Parallel and Distributed Computing (2013)

Tan Nguyen Daniel Hefenbrock Jason Oberg Ryan Kastner Scott B. Baden

Coprocessor

10.1016/j.jpdc.2013.01.012

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Citations (11)

TiDA: High-Level Programming Abstractions for Data Locality Management

Lecture notes in computer science (2016)

Didem Unat Tan Nguyen Weiqun Zhang Muhammed Nufail Farooqi Burak Bastem

10.1007/978-3-319-41321-1_7

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Citations (26)

SoC, NoC and Hierarchical Bus Implementations of Applications on FPGAs Using the FCUDA Flow

Tan Nguyen Yao Chen Kyle Rupnow Swathi Gurumani Yao Chen

The FCUDA project aims to improve programmability of FPGAs and expression of application parallelism in High Level Synthesis (HLS) through the use of the CUDA language. The CUDA language is a popular single-instruction multiple data (SIMD) style programming language with wide adoption, thus offering significant opportunity to bring experienced programmers to FPGA computing. The FCUDA project now has open-sourced the core CUDA to RTL transformation as well as the infrastructure for design space exploration, bus-based andNoC-based on-chip communications, and platform integration with Xilinx's SoC systems. In this paper, we present FCUDA's design space exploration, interconnect and platform integration to present guidelines for selecting system-level infrastructure for an application for the best implementation.

Implementation

SIMD

Design space exploration

High-Level Synthesis

10.1109/isvlsi.2016.131

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Citations (2)