This paper describes implementation of the 1.9GHz RF frequency synthesizer with silicon CMOS technology being used as an application of the USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with modulator, and common circuits of the PLL has been optimized. Especially to get good performance of speed, power consumption, and wide tuning range, N-P MOS core structure has been used in design of the VCO. The chip area including pads for testing is , and the chip area only core for IP in SoC is . The test results show that there is no special spurs except -63.06dB of the 6MHz reference spurs in the PLL circuitry. There is good phase noise performance like -116.17dBc/Hz in 1MHz offset frequency.
This paper presents a constant amplitude code division multiplexing scheme and the corresponding decoding algorithm for the IEEE 802.15.4g network (WPAN) standard for advanced utility service. The proposed scheme based on a turbo product code (TPC) consists of single parity check code and Hadamard code. Thus, an iterative TPC decoder can be exploited within a receiver for the proposed scheme. The proposed scheme offers constant amplitude output with low peak-to-average power ratio compared to conventional code division multiplexing schemes.
A fully integrated burst-mode upstream transmitter chip for gigabit-class passive optical network applications is implemented in 0.18mum CMOS technology. In order to control consecutive burst data, the transmitter proposed in this paper uses a reset mechanism with TX_enable as a burst envelope signal. The feedback from the monitoring photodiode (MPD) is separated by two independent paths for temperature compensation. The chip tested with chip-on-board configuration shows an average power of 2dBm with extinction ratio of above 12dB under 1.25Gb/s burst- mode operation. Based on the measurement, this work complies with the GPON ITU-T Recommendation G.984.2.
A selective internal reset mechanism that allows the burst-mode TIA to recover a burst-mode signal as a stand-alone device in EPON is discussed. Using step AGC, the TIA achieves a DR of 27dB and a sensitivity of -31dBm with a PIN photodiode. Moreover, with internal reset, the loud/soft ratio is also 27dB within 100ns guard and preamble times.
This paper describes implementation of the 5.0GHz RF frequency synthesizer with 0.18 silicon CMOS technology being used as an application of the IEEE802.15.4 USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with modulator, and common circuits of the PLL has been optimized. Especially to get excellent performance of high speed and wide tuning range, N-P MOS core structure and 12 step cap banks have been used in design of the VCO. The chip area including pads for testing is , and the chip area only core for IP in SoC is . Through analysing of the fabricated frequency synthesizer, we can see that it has wide operation range and excellent frequency characteristics.
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