Yufeng Guo

Nanjing University of Posts and Telecommunications

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i-10 index

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Jiafei Yao

Nanjing University of Posts and Telecommunications

Jun Zhang

Nanjing University of Posts and Telecommunications

Maolin Zhang

Nanjing University of Posts and Telecommunications

Weihua Tang

Nanjing University of Posts and Telecommunications

Zeng Liu

Inner Mongolia University

Jing Chen

Nanjing University of Posts and Telecommunications

Shan Li

Nanjing University of Posts and Telecommunications

Kemeng Yang

Nanjing University of Posts and Telecommunications

Changchun Zhang

Beijing Forestry University

Man Li

Nanjing University of Posts and Telecommunications

Cooperative Institutions

Nanjing University of Posts and Telecommunications

293

Chinese Academy of Sciences

225

University of Chinese Academy of Sciences

111

Beijing University of Posts and Telecommunications

Shanghai Jiao Tong University

Zhejiang University

Sun Yat-sen University

Tsinghua University

Peking University

Nanjing University

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A novel Hall dynamic offset cancellation circuit based on four-phase spinning current technique

China Semiconductor Technology International Conference (2015)

Xiaoqing Chen Yue Xu Xiaopeng Xie Yufeng Guo Yang Huang

A novel Hall dynamic offset cancellation circuit based on four-phase spinning current technique is introduced. The offset cancellation circuit of Hall sensor applies a novel configuration including four-phase spinning current modulator, instrumentation amplifier, correlated double sampling demodulator and adder, which effectively eliminate the offset and 1/f noise, and linearly amplify the Hall signal. Designed in 0.8 μm high voltage CMOS technology, the circuit simulation results show the residual offset is lower than 0.2 mT and the linearity is up to 99.9%.

Input offset voltage

Linearity

Correlated double sampling

DC bias

10.1109/cstic.2015.7153483

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Citations (3)

Automatic Design of Structural Parameters for GaN HEMT Using Genetic Algorithm and Artificial Neural Networks

Wei Du Jing Chen Jiahao Wu Qing Yao Yufeng Guo

10.1109/iseda62518.2024.10617532

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Citations (0)

Planning and Design Method of Distributed Harmonic Compensation in Power Grid Based on Active Power Filter Passive Device Margin Calculation Model

Shuyin Duan Xinting Luo Yufeng Guo Lei Yu Guoliang Huang

Harmonic

Active power filter

Harmonic Analysis

Margin (machine learning)

Power grid

10.1109/icpe59729.2023.10468936

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Hotspots and trends of risk factors in gastric cancer: A visualization and bibliometric analysis

World Journal of Gastrointestinal Oncology (2024)

Meng Li Ning Gao Shao-Li Wang Yufeng Guo Zhen Liu

The lack of specific symptoms of gastric cancer (GC) causes great challenges in its early diagnosis. Thus it is essential to identify the risk factors for early diagnosis and treatment of GC and to improve the survival rates.

10.4251/wjgo.v16.i5.2200

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Citations (0)

AFMPM: adaptive feature map pruning method based on feature distillation

International Journal of Machine Learning and Cybernetics (2023)

Yufeng Guo Weiwei Zhang Junhuang Wang Ji Ming Chenghui Zhen

Feature (linguistics)

Pruning

10.1007/s13042-023-01926-2

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Citations (2)

Tradeoff Between the Breakdown Voltage and Specific On-Resistance of SOI RESURF LDMOS

2021 IEEE 14th International Conference on ASIC (ASICON) (2023)

Yufeng Guo Kemeng Yang Jing Chen Man Li Zhengfei Jiang

The tradeoff between the breakdown voltage (BV) and specific on-resistance (R on,sp ) is an important issue for the power device. Baliga's Figure of Merits (BFOM) and silicon limit both are useful tools to evaluate this relationship. However, the strong 2-D effect is not considered in the conventional BFOM and the present silicon limit. In this paper, a new BFOM model of SOI RESURF LDMOS is proposed based on the formulized 2-D electric field in the drift region. Then, the device structure parameters are optimized to maximize the BFOM. A novel silicon limit and critical electric field are also derived. The differences between the lateral and the vertical devices are investigated and compared. The mechanism is discussed. The simulation based on the TCAD tool is employed to verify the novel BFOM and silicon limit.

LDMOS

Power MOSFET

10.1109/asicon58565.2023.10396435

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Citations (2)

Shelterbelt-farmland differences in P fractions interacted with soil alkalization, geoclimatic conditions, and soil fungi in Northeast China Plain

Journal of Soils and Sediments (2023)

Meina Zhu Yufeng Guo Xudong Cao Yanbo Yang Qian Du

Windbreak

10.1007/s11368-023-03551-6

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Citations (2)

A current model for FOI FinFETs with back-gate bias modulation

Solid-State Electronics (2021)

Fanyu Liu Xingyun Zhang F.Y. Zhang Bo Li Bing Li

Fin

10.1016/j.sse.2021.108095

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Citations (2)

Design and Implementation of Henan Huinong Client System Based on iOS

ITM Web of Conferences (2016)

Yan‐Ling Li Zhang Li Yufeng Guo Lei Xi Changxia Sun

In order to meet the demands of customers related to agriculture who can obtain some Comprehensive agricultural information service of Henan Province through the intelligent mobile terminal, on the base of the Zhong yuan Rural Information Port integrated platform, employing IOS, Java, Eclipse, XML, SAX technology, we designed and developed Henan Huinong client systems based on ios mobile terminal. This system has achieved the multiple applications, such as agricultural information browsing, network consulting, expert online, crop rermote diagnosis and so on.

Port (circuit theory)

Mobile phone

Eclipse

10.1051/itmconf/20160701007

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Citations (0)

A 32.2 GHz Full Adder Designed with TLE Method in a InP DHBT Technology

JSTS Journal of Semiconductor Technology and Science (2021)

Yi Zhang Xiaopeng Li Youtao Zhang Yufeng Guo Ying Zhang

Ultra-high-speed full adder is the bottleneck in a tens of GHz Direct digital synthesizer (DDS). In this paper, a 32.2 GHz, 1bit full adder in a 0.7 μm InP double hetero-junction bipolar transistor (DHBT) technology is presented. In such a high-speed circuit, signal integrity is a crucial issue. Therefore, a transmission line equivalent (TLE) method is proposed. With the TLE method, the design of the full adder could be simplified with good accuracy. The synchronous latch is combined with adding operation to improve the calculation speed. A single-level parallel-gated circuit is designed using majority decision algorithm to reduce power consumption. Measurement results show that the maximum clock frequency of the full adder is 32.2-GHz, and the overall power consumption is 350 mW. The full adder is successfully adopted in a 17 GHz, 8 bit DDS which can synthesize sin-wave outputs from 66.41 MHz to 8.5 GHz in 66.41 MHz steps with an average Spurious-Free Dynamic Range (SFDR) of -18.1 dBc.

Spurious-free dynamic range

Heterojunction bipolar transistor

Serial binary adder

10.5573/jsts.2021.21.6.438

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Citations (1)