Ferroelectric diodes can generate a polarization-controlled bidirectional photoresponse to simulate inhibition and promotion behaviors in the artificial neuromorphic system with fast speed, high energy efficiency, and nonvolatility. However, the existing ferroelectric diodes based on ferroelectric oxides suffer from a weak bidirectional photoresponse (below 1 mA/W), difficult miniaturization, and a large response photon energy (over 3 eV). Here, we design a series of van der Waals $\ensuremath{\alpha}\text{\ensuremath{-}}{\mathrm{In}}_{2}{\mathrm{Se}}_{3}\text{/}\mathrm{Nb}{X}_{2}$ ($X$ = S, Se, and Te) ferroelectric diodes with bidirectional photoresponse by using ab initio quantum transport simulation. These devices show a maximum bidirectional photoresponse of 30 (\ensuremath{-}19) mA/W and a minimum response photon energy of 1.3 eV at the monolayer thickness. Our work shows advanced optoelectronic applications of the van der Waals ferroelectric diodes in the future artificial neuromorphic system.
With the scaling limits of silicon-based MOS technology, the critical and challenging issue is to explore more and more alternative materials to improve the performance of devices. Two-dimensional (2D) semiconductor WSe2 with a proper band gap and inherent stability under ambient conditions makes it a potential channel material for realizing new generation field-effect transistors (FETs). In light of the low on-state current of the experimental sub-10 nm 2D MoS2 FETs, we explore the limitation of the monolayer (ML) WSe2 device performance by using accurate ab initio quantum transport simulation. We find that the sub-10 nm 2D WSe2 FETs apparently outperform their MoS2 counterpart. The on-state current of the optimized p-type ML WSe2 FETs can satisfy the criteria of the International Technology Roadmap for Semiconductors (ITRS) on both the high-performance (HP) and low-power (LP) devices until the gate length is scaled down to 2 and 3 nm, respectively. By the aid of the negative capacitance effect, even the 1 nm gate-length WSe2 MOSFETs can satisfy both the HP and LP requirements in the ITRS 2028 completely. Remarkably, the ML WSe2 MOSFET has the highest theoretical on-current in LP application among the examined 2D MOSFETs at the 5 nm gate length to the best of our knowledge.
Identification of size effects at an atomic level is essential for designing high-performance metal-based catalysts. Here, the performance of a series of FeOx-supported Pt catalysts with Pt as nanoparticles (Pt-NP) or single atoms (Pt-SAC) are compared for the low-temperature water-gas shift (WGS) reaction. A variety of characterization methods such as adsorption microcalorimetry, H2-TPR, in situ DRIFTS, and transient analysis of product tests were used to demonstrate that Pt nanoparticles exhibit much higher adsorption strength of CO; the adsorbed CO reacts with the OH groups, which are generated from activated H2O, to form intermediate formates that subsequently decompose to produce CO2 and H2 simultaneously. On the other hand, Pt single atoms promote the formation of oxygen vacancies on FeOx which dissociate H2O to H2 and adsorbed O that then combines with the weakly adsorbed CO on these Pt sites to produce CO2. The activation energy for the WGS reaction decreases with the downsizing of Pt species, and Pt-SAC possesses the lowest value of 33 kJ/mol. As a result, Pt-SAC exhibits 1 order of magnitude higher specific activity in comparison to Pt-NP. With a loading of only 0.05 wt % the Pt-SAC can achieve ∼65% CO conversion at 300 °C, representing one of the most active catalysts reported so far.
Abstract Over the past decade, two-dimensional semiconductors (2DSCs) have aroused wide interest due to their extraordinary electronic, magnetic, optical, mechanical, and thermal properties, which hold potential in electronic, optoelectronic, thermoelectric applications, and so forth. The field-effect transistor (FET), a semiconductor gated with at least three terminals, is pervasively exploited as the device geometry for these applications. For lack of effective and stable substitutional doping techniques, direct metal contact is often used in 2DSC FETs to inject carriers. A Schottky barrier (SB) generally exists in the metal–2DSC junction, which significantly affects and even dominates the performance of most 2DSC FETs. Therefore, low SB or Ohmic contact is highly preferred for approaching the intrinsic characteristics of the 2DSC channel. In this review, we systematically introduce the recent progress made in theoretical prediction of the SB height (SBH) in the 2DSC FETs and the efforts made both in theory and experiments to achieve low SB contacts. From the comparison between the theoretical and experimentally observed SBHs, the emerging first-principles quantum transport simulation turns out to be the most powerful theoretical tool to calculate the SBH of a 2DSC FET. Finally, we conclude this review from the viewpoints of state-of-the-art electrode designs for 2DSC FETs.
The gate-all-around (GAA) $\mathrm{Si}$ nanowire (NW) field-effect transistor (FET) is considered one of the most promising successors of the current mainstream $\mathrm{Si}$ fin FET (FinFET) owing to its better electrostatic gate control. Experimentally, the diameter of $\mathrm{Si}$ NWs has been scaled down to 1 nm. In this paper, the performance limit of the GAA $\mathrm{Si}$ NWFET with a 1-nm diameter is investigated by utilizing ab initio quantum transport simulations. We prove that the electrical conduction is concentrated in the core of the ultranarrow wire channel. The minimum gate length (${L}_{g}$) at which the n- and p-type GAA $\mathrm{Si}$ NWFET can satisfy the high-performance application requirements (on-state current, gate capacitance, delay time, and power dissipation) of the International Technology Roadmap for Semiconductors is 3 nm. The best-performing 5-nm-${L}_{g}$ n-type GAA $\mathrm{Si}$ NWFET exhibits an energy-delay product comparable with typical monolayer two-dimensional FETs. Compared with the similar-sized trigate $\mathrm{Si}$ NW FinFET, an approximately 200% increase in the on-state current and about 15% decrease in the subthreshold swing are witnessed in GAA $\mathrm{Si}$ NWFET at the same 5-nm ${L}_{g}$. Through strain engineering, about an 80% increase of on-state current is observed in the 5-nm-${L}_{g}$ p-type GAA $\mathrm{Si}$ NWFET. Our research demonstrates the vast potential of the GAA $\mathrm{Si}$ NWFET in the sub-3-nm gate-length region.
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