Shuming Chen

National University of Defense Technology

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Biwei Liu

National University of Defense Technology

Bin Liang

Nanjing University

Jianjun Chen

National University of Defense Technology

Yaohua Wang

National University of Defense Technology

Pengcheng Huang

National University of Defense Technology

Jianghua Wan

Harbin Institute of Technology

Jun-Rui Qin

National University of Defense Technology

Shenggang Chen

Beijing Forestry University

Zhonghai Lu

KTH Royal Institute of Technology

Zhenyu Wu

Beijing Chao-Yang Hospital

Cooperative Institutions

National University of Defense Technology

110

Chinese Academy of Sciences

Tsinghua University

Huazhong University of Science and Technology

Hunan University

University of Chinese Academy of Sciences

Beijing Jiaotong University

Zhejiang University

Institute of Microelectronics

Sun Yat-sen University

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Simulation-Based Hardware Verification with a Graph-Based Specification

Mathematical Problems in Engineering (2018)

Zhao Lv Shuming Chen Yaohua Wang

Simulation-based verification continues to be the primary technique for hardware verification due to its scalability and ease of use; however, it lacks exhaustiveness. Although formal verification techniques can exhaustively prove functional correctness, they are limited in terms of the scale of their design due to the state-explosion problem. Alternatively, semiformal approaches can involve a compromise between scalability, exhaustiveness, and resource costs. Therefore, we propose an event-driven flow graph-based specification, which can describe the cycle-accurate functional behaviors without the exploration of whole state space. To efficiently generate input sequences according to the proposed specification, we introduce a functional automatic test pattern generation (ATPG) approach, which involves the proposed intelligent redundancy-reduction strategy to solve problems of random test vectors. We also proposed functional coverage criterion based on the formal specification to support a more reliable measure of verification. We implement a verification platform based on the proposed semiformal approach and compare the proposed semiformal approach with the constrained randomized test (CRT) approach. The experiment results show that the proposed semiformal verification method ensures a more exhaustive and effective exploration of the functional correctness of designs under verification (DUVs).

Functional verification

High-level verification

Runtime Verification

Partial order reduction

10.1155/2018/6398616

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DSBS: Distributed and Scalable Barrier Synchronization in Many-Core Network-on-Chips

Xiaowen Chen Shuming Chen

This paper proposes a distributed and scalable hardware solution for efficient barrier synchronization management on many-core Network-on-Chips (NoCs). It includes two hardware modules, named Root Distributed and Scalable Barrier Synchronizer (Root DSBS) and Leaf Distributed and Scalable Barrier Synchronizer (Leaf DSBS). The Root DSBS is located in the central node, connecting to the processor core and the network interface. It provides a set of globally addressed barrier counters, sets the barrier and counts arriving "barrier acquire" requests, and releases the barrier and sends out "barrier release" acknowledgements once the barrier condition is satisfied. The Leaf DSBS is integrated into each router in the on-chip network. It is responsible for efficiently transmitting barrier synchronization related packets in the on-chip network to the Root DSBS. The Root DSBS in the central node and all Leaf DSBSs in routers cooperate together to accomplish barrier synchronization. Our solution has two salient features. One is called "Unicast Merging" - "barrier acquire" packets towards the same barrier are merged into one packet when they pass through the same router simultaneously. The purpose is to minimize the completion time of barrier acquiring by reducing the number of barrier synchronization related packets. The other is called "Broadcasting" - a "barrier release" packet is broadcasted to all synchronized nodes. Its object is to reduce area cost by avoiding storing synchronized node numbers as well as to minimize the completion time of barrier releasing by avoiding sending unicast "barrier release" packets. To evaluate the performance, we investigate hardware cost and employ both synthetic and application experiments. Synthesis and experiment results show that our distributed and scalable barrier synchronization obtains both area and performance advantage over the conventional barrier synchronization counterpart. The Root DSBS and Leaf DSBSs can run over 2GHz in TSMC ^® 65nm technology with small area overhead. Our solution only costs a little completion time and generates well distributed and uniform network traffic. When the network size is 16×16, the application's performance improvement can achieve 24.60%.

Synchronizer

Unicast

Network interface

10.1109/trustcom.2011.141

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Citations (3)

Calculating the Soft Error Vulnerabilities of Combinational Circuits by Re-Considering the Sensitive Area

IEEE Transactions on Nuclear Science (2014)

Shuming Chen Yankang Du Biwei Liu Jun-Rui Qin

Concepts of effective sensitive area and effective SET pulse width are proposed to model the actual sensitive area. Simulation results present that the soft error vulnerabilities got by using the effective sensitive area can be almost an order larger than the ones got by using the normal approach when the ion LET is 30 MeV ·cm ² /mg. And heavy-ion experiments are conducted to demonstrate the simulation results.

Soft error

10.1109/tns.2014.2298889

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Citations (25)

Cooperative communication for efficient and scalable all-to-all barrier synchronization on mesh-based many-core NoCs

IEICE Electronics Express (2014)

Xiaowen Chen Zhonghai Lu Axel Jantsch Shuming Chen Yang Guo

On many-core Network-on-Chips (NoCs), communication is on the critical path of system performance and contended synchronization requests may cause large performance penalty. Different from conventional algorithm-based approaches, the paper addresses the barrier synchronization problem from the angle of optimizing its communication performance and proposes cooperative communication as a means to achieve efficient and scalable all-to-all barrier synchronization on mesh-based many-core NoCs. With the cooperative communication, routers collaborate with one another to accomplish a fast barrier synchronization task. The cooperative communication is implemented in our router at low cost. Through comparative experiments, our approach evidently exhibits high efficiency and good scalability.

Mesh networking

10.1587/elex.11.20140542

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Citations (3)

Radiation hardened by design techniques to reduce single event transient pulse width based on the physical mechanism

Microelectronics Reliability (2012)

Jianjun Chen Shuming Chen Bin Liang Biwei Liu Fanyu Liu

Transient (computer programming)

10.1016/j.microrel.2011.12.002

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Citations (42)

The Analysis of Idiom Translation in chinese Translated novel "Narnia: The Magician's Nephew"

Shuming Chen Hsin-yi Chan

Nephew and niece

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Hot carrier effects of SOI NMOS

Journal of Semiconductors (2010)

Jianjun Chen Shuming Chen Bin Liang Biwei Liu Liu Zheng

Hot carrier effect (HCE) is studied on annular NMOS and two-edged NMOS such as H-shape gate NMOS, T-shape gate NMOS and common two-edged NMOS. Based on the chemical reaction equation of HCE degradation and a geometry dependent reaction diffusion equation, a HCE degradation model for annular NMOS and two-edged NMOS is proposed. According to this model, we conclude that the time exponent of the threshold voltage degradation depends on the configuration of the gate, and annular NMOS has more serious HCE degradation than two-edged NMOS. The design, fabrication and HCE experiments of these NMOS in a 0.5-μm PD SOI process verify the correctness of the conclusion.

Degradation

10.1088/1674-4926/31/7/074006

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Citations (8)

Propagation-constant matching based broadband permittivity extraction from S-parameter

IEICE Electronics Express (2015)

Xi Ning Shuming Chen Lei Wang

This paper presents a coplanar waveguide (CPW) method to extract the permittivity of dielectric materials. The extraction is implemented by specifying an estimated permittivity and then calibrating it repeatedly. The calibrating process lies on matching the simulated and measured propagation-constants, i.e., narrowing their difference until it is less than 1%. A single variable strategy is also proposed to accelerate the calibration. Compared with the transmission-line method, our method shows good agreement over a broad frequency range for silicon substrate, while it is easier to be implemented.

Propagation constant

Coplanar waveguide

Constant (computer programming)

10.1587/elex.12.20150463

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Loop Buffering:An Effective Method to Reduce the Power Consumption of Instruction Memory

Computer Engineering and Science (2007)

Shuming Chen

For digital processing processors with the Very Long Instruction Word (VLIW) architecture, a significant amount of power is consumed in instruction memories. According to the characteristics of digital processing applications, loop buffering can be used to reduce the power consumption of instruction memories while fetching instructions. This paper presents a low power compilation method based on the compiler-controlled loop buffer where the compiler is responsible for selecting appropriate loops and putting them into the buffer.The paper gives an analysis of the power dissipation and architectural design of the loop buffer,and a compilation method to use the loop buffer effectively.Finally, the effectiveness of the proposed method is validated by a function-level power analysis model.

Write buffer

Power analysis

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Speedup analysis of data-parallel applications on Multi-core NoCs

Xiaowen Chen Zhonghai Lu Axel Jantsch Shuming Chen

As more computing cores are integrated onto a single chip, the effect of network communication latency is becoming more and more significant on multi-core network-on-chips (NoCs). For data-parallel applications, we study the model of parallel speedup by including network communication latency in Amdahl's law. The speedup analysis considers the effect of network topology, network size, traffic model and computation/communication ratio. We also study the speedup efficiency. In our multi-core NoC platform, a real data-parallel application, i.e. matrix multiplication, is used to validate the analysis. Our theoretical analysis and the application results show that the speedup improvement is nonlinear and the speedup efficiency decreases as the system size is scaled up. Such analysis can be used to guide architects and programmers to improve parallel processing efficiency by reducing network latency with optimized network design and increasing computation proportion in the program.

Speedup

10.1109/asicon.2009.5351597

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Citations (12)