Dongsheng Liu

Huazhong University of Science and Technology

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Xuecheng Zou

Wuhan National Laboratory for Optoelectronics

Jiahao Lu

Huazhong University of Science and Technology

Ang Hu

Huazhong University of Science and Technology

Zirui Jin

University of Science and Technology of China

Aobo Li

Nanyang Technological University

Kefeng Zhang

Santa Monica College

Ang Hu

Huazhong University of Science and Technology

Xueqiu Wang

Chinese Academy of Geological Sciences

Bimin Zhang

Chinese Academy of Geological Sciences

Hanliang Liu

Chinese Academy of Geological Sciences

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Huazhong University of Science and Technology

178

Chinese Academy of Sciences

Shanghai Jiao Tong University

University of Chinese Academy of Sciences

Wuhan National Laboratory for Optoelectronics

Wuhan University of Technology

Chinese Academy of Geological Sciences

Peking University

University of Science and Technology of China

Sun Yat-sen University

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New design of sense amplifier for EEPROM memory

Journal of Zhejiang University. Science A (2009)

Dongsheng Liu Xuecheng Zou Qiong Yu Fan Zhang

EEPROM

Sense amplifier

Direct-coupled amplifier

10.1631/jzus.a0820262

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Citations (3)

A Low-Cost Low-Power Ring Oscillator-Based Truly Random Number Generator for Encryption on Smart Cards

IEEE Transactions on Circuits & Systems II Express Briefs (2016)

Dongsheng Liu Zilong Liu Lun Li Xuecheng Zou

The design of a low-cost low-power ring oscillator-based truly random number generator (TRNG) macrocell, which is suitable to be integrated in smart cards, is presented. The oscillator sampling technique is exploited, and a tetrahedral oscillator with large jitter has been employed to realize the TRNG. Techniques to improve the statistical quality of the ring oscillatorbased TRNGs' bit sequences have been presented and verified by simulation and measurement. A postdigital processor is added to further enhance the randomness of the output bits. Fabricated in the HHNEC 0.13-μm standard CMOS process, the proposed TRNG has an area as low as 0.005 mm ² . Powered by a single 1.8-V supply voltage, the TRNG has a power consumption of 40 μW. The bit rate of the TRNG after postprocessing is 100 kb/s. The proposed TRNG has been made into an IP and successfully applied in an SD card for encryption application. The proposed TRNG has passed the National Institute of Standards and Technology tests and Diehard tests.

Ring oscillator

10.1109/tcsii.2016.2530800

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Citations (78)

DSET-Net: deep self-embedded transformer network for hyperspectral unmixing

Xueer You Yuanchao Su Lianru Gao Xu Sun Pengfei Li

Recently, transformer self-attention mechanisms have had significant advantages in the deep learning field, and it has been extensively used for natural language processing and video tracking. Furthermore, self-attention mechanisms have also been applied in hyperspectral unmixing. Although self-attention mechanisms are usually efficient and flexible tools, the original transformer might break the inner structure of data during learning, causing negative effects to unmixing. In this work, we employ transformer self-attention mechanisms to achieve a deep self-embedded transformer network(DSET-Net) for hyperspectral unmixing. The proposed DSET-Net adopts an autoencoder framework and achieves local and overall feature parameter sharing in the encoder through a 'Transformer in Transformer (TNT)' strategy. The DSET-Net preserves the spatial details of hyperspectral images and involves only one convolution operation in the encoder, substantially improving the learning performance. The effectiveness of the proposed method is evaluated by using real hyperspectral datasets. Our experimental results indicate that the newly proposed DSET-Net is very competitive compared with other state-of-the-art approaches.

Autoencoder

Feature Learning

10.1117/12.3019479

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Effect of Dietary Lactobacillus plantarum Supplementation on the Growth Performance, Intestinal Health, Antioxidant Capacity, and mTOR Signaling Pathway of Juvenile Coho Salmon (Oncorhynchus kisutch)

International Journal of Molecular Sciences (2025)

Qin Zhang Lan Li Rongxin Qin Liuqing Meng Dongsheng Liu

This study investigates the effect of dietary Lactobacillus plantarum supplementation on juvenile coho salmon (Oncorhynchus kisutch). Four groups of the juveniles (initial weight 103.87 ± 2.65 g) were fed for 10 weeks with four diets containing 0 (control diet), 105 (T1), 107 (T2), and 109 (T3) cfu/g of L. plantarum. The main results are as follows: Compared with the control diet, the final weight, specific growth rate (SGR), and weight gain rate (WGR) of the juveniles fed the T1, T2, and T3 diet significantly (p < 0.05) increased, while the feed coefficient ratio (FCR) expressed an opposite trend. The activities of superoxide dismutase (SOD), catalase (CAT), and glutathione peroxidase (GSH-PX) in the serum of the juveniles fed the T2 diet significantly (p < 0.05) increased, while the malondialdehyde (MDA) expressed an opposite trend. The expression of phosphatidylinositol 4,5-bisphosphate 3-kinase (pi3k), AKT-interacting protein (akt), mechanistic target of rapamycin kinase (mtor), glucose-6-phosphate dehydrogenase (g6pd), sod, cat, and gsh-px genes in the liver of the juveniles fed the T2 diet significantly (p < 0.05) increased. In conclusion, the T2 diet significantly improved the growth performance, antioxidant capacity, and upregulated key mTOR pathway genes in juvenile coho salmon.

Malondialdehyde

10.3390/ijms26030907

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Plagiarism detection algorithm based on XML for C code

Computer Engineering and Applications Journal (2011)

Dongsheng Liu

This paper mainly studies a plagiarism detection algorithm based on XML for C code.It generates a XML text from C source code,extracts the structure information of XML text lines,calculates the XML text lines similarity and obtains the similarity of two programs.Plagiarism detection algorithm is implemented to classification test,specific categories are described as follows:the means of 12 kinds’plagiarism,complex semantics and complex data structures.Test results verify the effectiveness of plagiarism detection algorithm.

Plagiarism detection

Code (set theory)

Similarity (geometry)

XML Schema (W3C)

Source

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A 433/2400 MHz dual-band frequency synthesizer with glitch-free phase-interpolated frequency divider and hybrid post-synthesizer

Microelectronics Journal (2021)

Xiaoke Tang Xu Zhao Ang Hu Dongsheng Liu Zirui Jin

A three-stage low phase noise cascaded phase locked loop (PLL) with reference quadrupler and phase-interpolated (PI) frequency divider is presented in this paper. The first stage consists of a frequency doubler and an injection locked (IL) loop. By increasing the reference frequency from 50 MHz to 200 MHz, the maximum loop division ratio is deduced, yielding to 12 dB in-band noise transfer gain suppression and larger loop bandwidth. The second stage is a fractional-N PLL. In order to mitigating the effect of quantization noise in fractional-N model, a double-orthogonal PI frequency divider is utilized. The division ratio step is reduced from 1 to 1/32, leading to 30 dB quantization noise suppression. The third stage is a hybrid charge-pump (CP) and sub-sampling PLL (SSPLL). By utilizing this hybrid structure, the third-stage output phase noise is dominated by the output clock of the second stage. The PLL is designed and simulated in 65 nm CMOS process. At 2.4 GHz, the spot phase noise are −100 and −114 dBc/Hz at 10 kHz and 1 MHz offsets respectively and the power consumption is 12 mW.

Frequency multiplier

dBc

PLL multibit

10.1016/j.mejo.2021.105158

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Citations (4)

A 0.4-to-0.8 V 0.1-to-5 MS/s 10 b two-step SAR ADC with TDC-based fine quantizer in 40-nm CMOS

Microelectronics Journal (2023)

Chengcheng Zhang Ang Hu Dongsheng Liu Shuo Ma Hao Li

This paper presents an energy efficient two-step hybrid-domain successive approximation register (SAR) analog-to-digital converter (ADC). Comparator offset calibration and kickback noise reduction techniques are proposed to maintain the high dynamic range and elevated residual signal quality of the coarse ADC. A feedback adjustment technology is proposed to reduce energy consumption of voltage-to-time converter (VTC). The VTC offset and LSB gain error between the coarse ADC and fine time-to-digital converter (TDC) are calibrated to ensure the gain accuracy. The proposed SAR ADC is designed in a 40-nm CMOS process and occupies 0.0363 mm2 silicon area. The post-simulation results show the proposed ADC achieved a spurious-free dynamic range (SFDR) of 74.8 dB and a signal-to-noise and distortion ratio (SNDR) of 56.42 dB at 0.4 V supply voltage and Nyquist input rate. The operating frequency scales from 100 kS/s to 5 MS/s. The converter has a power supply range of 0.4–0.8 V, and the figure of merit (FOM) is 4.85–10.6 fJ/conversion step.

Spurious-free dynamic range

Successive approximation ADC

Nyquist rate

Figure of Merit

Nyquist frequency

10.1016/j.mejo.2023.105974

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Citations (4)

ASANet: Asymmetric Semantic Aligning Network for RGB and SAR image land cover classification

ISPRS Journal of Photogrammetry and Remote Sensing (2024)

Pan Zhang Baochai Peng Chaoran Lu Quanjin Huang Dongsheng Liu

Land Cover

RGB color model

10.1016/j.isprsjprs.2024.09.025

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A DTC-based Fractional-N DPLL using probability-density-shaping spur immunity and Q-noise reduction techniques for IoT applications

Microelectronics Journal (2023)

Zirui Jin Xiaoyu Shan Ang Hu Dongsheng Liu Xuan Cheng

A Digital-to-Time Converter based (DTC-based) fractional-N digital phase-locked loop (DPLL) using probability-density-shaping (PDS) spur immunity and quantization phase (Q-noise) reduction techniques is presented. PDS-DSM is used to generate a loop spur immunity control code for DTC. A diff type dither is proposed to further suppress the fractional spur. The loop nonlinearity will not cause fractional spurs if certain conditions are obeyed. Moreover, to reduce the quantization noise, a configurable Phase Interpolator (PI) with 0.125/0.25/0.5/1.0 division step is integrated with a multi-module divider (MMDIV), leading to an 18-dB Q-noise suppression. A reference doubler with duty-cycle correction is adopted to further reduce phase noise. The fractional spurs are greatly mitigated by combining the PDS-DSM and phase interpolator. A DPLL prototype using the aforementioned techniques was designed in a 40-nm standard CMOS process, occupying a 0.99 mm2 silicon area. At a near-integer-N frequency, i.e., near 2.23 GHz, with PDS turned on and off, the post-layout simulated fractional spur is −59 dBc and −20 dBc, respectively. The RMS jitter of the whole chip is 4.218 ps, corresponding to a figure of merit (FOM) of −220.5 dB.

Spur

DPLL algorithm

dBc

10.1016/j.mejo.2023.105753

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Citations (2)

An analog front-end circuit for ISO/IEC 15693-compatible RFID transponder IC

Journal of Zhejiang University. Science A (2006)

Dongsheng Liu Xuecheng Zou Qiu-ping Yang Ting-wen Xiong

Transponder (aeronautics)

Analog front-end

10.1631/jzus.2006.a1765

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Citations (7)