This paper proposes a novel dopingless ternary FET (DLT-FET) composed of the longitudinal metal-source/InAs-channel/InAs-drain structure for compact implementation of the ternary inverter. A single DLT-FET mixes two types of carrier transport mechanisms: 1) according to the concept of charge plasma, the Band-to-Band tunneling (BTBT) can occur at channel/drain interface by metal work function engineering; 2) Schottky Barrier tunneling (SBT) at the source/channel interface. The mechanism of the DLT-FET is verified with the help of TCAD tools. The simulation results revealed that both N/P-type DLT-FETs have a flat drain current characteristic around V G = 0.5 V DD , where the V G -independent I BTBT dominates the drain current. The stable third output voltage can be obtained through the voltage dividing, while both the I SBT and I BTBT generate the other voltage levels of 0 V and 1.0 V DD . Furthermore, the effects of a series of key device parameters on DLT-FETs and ternary inverter performance are evaluated. The ternary inverter can be implemented by simply replacing two transistors with N/P-type DLT-FETs in a conventional binary inverter and selecting appropriate device parameters for exhibiting comparable transfer characteristics.
This study presents a technique for designing a multimode configurable weak physically unclonable function (PUF) for security-key generation. The PUF cell is based on the maximum gain point deviations of bias-voltage-controlled inverters. By implementing a preselection strategy, the proposed PUF can simultaneously expose all unstable cells under normal voltage and temperature. Owing to the configurable bias circuit, the PUF cell can be biased at three operating modes, namely, traditional inverter (INV), current-starved inverter (CSI), and power gating (PG). The measurement results from a 65-nm prototype show that the proposed PUF has the following outstanding features: 1) it has a compact cell layout with a minimum feature size of 966 F2; 2) an autocorrelation function of 0.0099 is achieved; and 3) all unstable cells can be eliminated using a preselection procedure, which can drastically reduce the energy and area costs for error correction. In addition, in the CSI mode, the proposed PUF (standard voltage) has maximum frequency and throughput of 714 MHz and 45.7 Gb/s, respectively. Meanwhile, under the INV mode, the worst native bit error rate (low voltage) for 5000 evaluations is only 0.33%, indicating a desirable instability against voltage and temperature variations with a sensitivity coefficient of 1.85%/V and 0.018%/°C, respectively. Moreover, the measured energy efficiency at 0.6 V is 6.83 fJ/bit. Finally, under the PG mode, the standby powers at 0.6 and 1.2 V are only 18 and 86 nW, respectively.
Physical unclonable function (PUF) has emerged as a lightweight hardware security primitive for resource constrained devices. The arbiter PUF (APUF) is a typical kind of strong PUF. However, conventional APUF is vulnerable to machine learning (ML) attacks. In this paper, we propose an obfuscated challenge design for APUF (OC-APUF), which exchanges the bit positions in the challenge according to our design rules. The subsequent recovery of the obfuscated challenge by a recovery circuit is guaranteed. Then the corresponding response is produced by the APUF with the real challenge. The goal is to obscure the direct relationship between challenges and responses to prevent ML attacks. Most importantly, the unclonability of the APUF is preserved, and there is almost no increase in hardware complexity while still maintaining a high level of security. Experiment results show that 64-bit APUF with obfuscated challenge can resist ML attacks with a maximum prediction rate of 60% using the logistic regression (LR) strategy.
Arbiter Physical Unclonable Function (APUF), as a typical representative of strong PUF, suffers from limitations in hardware cost and randomness, severely constraining its application in the field of resource-constrained Internet of Things (IoT). This paper investigated the mechanism of MOSFET threshold loss and proposed a lightweight strong APUF structure of two kinds of MOSFETs. This structure utilizes the threshold loss that occurs when PMOS transmits low level and NMOS transmits high level, greatly extending the delay deviation of the rising and falling edges, thus enhancing the randomness of the PUF and passing 9 NIST randomness subtests. Each delay unit of the two proposed PUF circuits consists of only 16 MOS transistors, which is 8 transistors less than the delay unit of APUF. The full-custom layout area of the proposed delay unit is 4.68 μm 2 in TSMC 65 nm process, reducing the area by 35.8% compared to the traditional APUF.
The micromagnetometers with high-resolution digital output are widely used in military and civilian fields. We proposed a novel high-precision interface circuit with an optimized chopper technique and switched-capacitor (SC) modulator for tunneling magnetoresistance (TMR) sensors. This work also proposes a novel method to create a lightweight physically unclonable function (PUF) by using existing TMR devices. The sigma-delta modulator converts the sensor signal into a robust digital output and maintains the signal-to-noise ratio (SNR) of the front-end circuit. We also take advantage of inherent variations of TMR sensors to generate PUF responses that are similarly unique and unclonable. The interface circuit is fabricated by a 0.35- $\mu \text{m}$ CMOS process from the Shanghai Huahong foundry. The active area of ASIC is only about $3\times2.7$ mm. The interface circuit can achieve an SFDR of 120 dB and an SNR of 98 dB at a sampling frequency of 200 kHz. The TMR magnetometers were tested in an environment of three-layer magnetic shielding. Our proposed PUF is also tested in terms of uniqueness and reliability.
The physical unclonable function (PUF) can generate a unique identifier for each chip, ideal for key generation and chip anti-counterfeiting. The reliability of PUF is paramount, and therefore is one of the significant challenges for PUF design. This brief proposes a novel SRAM- and Inverter-based PUF (SI PUF) that can operate as either an SRAM PUF or an inverter PUF, depending on the input configuration signal. A zero-overhead bit configuration strategy (BCS) is proposed to enhance the reliability of PUF. Moreover, the working voltage of the sub-threshold level and the well-designed discharge stage ensure that our SI PUF can operate with low power consumption. The tested results of chips fabricated in 40-nm CMOS show that our SI PUF has only 0.0053% of the worst bit error rate (BER) under working conditions of −50 to 125°C and 0.75 to 1.5V, with 0.073/0.042 pJ/bit of power consumption. The low BER and energy overhead illustrate that our SI PUF is more suitable for resource-limited devices compared to DAC 2022 and JSSC 2020.
Owing to the large area and power consumption of traditional physically unclonable function (PUF) circuits, they are susceptible to interference from environmental factors. A compact PUF circuit design scheme is proposed by analyzing the circuit structure and sub-threshold leakage current deviation characteristics of a bistable PUF. First, the current-voltage sensitive characteristics of a transistor in the sub-threshold operating region are utilized. Next, to improve the output response speed and the uniqueness of the characteristic information of the PUF circuit, the proposed PUF circuit is designed which combines with the positive feedback and RS latch characteristics. Finally, simulation results based on the TSMC 65nm CMOS process show that the PUF has good uniqueness, randomness, and reliability. The cell layout area, the bit error rate (BER) in the worst case, and the energy consumption are 0.177µm2, 2.8%, and 8.976fJ/bit respectively.
The Internet of Things (IoT) plays an important role in all aspects of production and day-to-day life. However, owing to the frequently trusted authentication vulnerabilities, the physical unclonable function (PUF) has unique advantages in the field of equipment authentication because of its nonstorage and nonvolatility. Nevertheless, PUFs are vulnerable to machine learning (ML) attacks. Once a model is constructed accurately, the secrecy of the PUF is lost. Therefore, Bagua matrices are proposed in this study, which can greatly reduce the accuracy of modeling by encrypting the challenge information. On this basis, a whole-process configurable IoT sensing device protocol was constructed for authentication and transmission, and different matrix encryption methods were configured according to the needs of the different devices. Moreover, on the premise of trusted authentication, the perceptual information can be encrypted using a preset matrix. According to the implementation results of the scheme, the resistance to the ML attacks of the PUF improved significantly and the device authentication and encrypted transmission could operate normally.
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