A transimpedance amplifier fabricated in a 0.13 µm CMOS process that operates at bit rates up to 25 Gbit/s with a power consumption of 0.36 mW/Gbit/s is reported. The amplifier provides 42 dBΩ of transimpedance gain over a 15 GHz bandwidth and exhibits a bit-error-ratio of less than 10−12 for peak-to-peak input currents of 225 and 425 µA at 20 and 25 Gbit/s, respectively.
Abstract SRAM is often chosen to be the process qualification vehicle during technology development or yield learning vehicle during product manufacturing, and consequently failure analysis of SRAM is the main feedback for process improvement and yield learning. The most common SRAM failure is single bit cell failure. Although its location can be precisely localized by functional test and the defect causing the failure is within the failing bit cell, its failure analysis becomes more and more challenging in advanced technology nodes. As semiconductor technology continuously scales down, SRAM bit cell size and power supply voltage decrease, resulting in increased transistor strength variation and mismatch. SRAM single bit cell soft failures have become more and more common. For such a failure, its defect is usually subtle or even there is not physical defect at most cases. The soft failure is just due to transistor parameter variation. To evaluate the single bit cell soft failure and identify its root cause, electrical nano-probing is an indispensable measure. In this paper, we will first describe the operation of a 6-Transistor (6-T) SRAM single bit cell and three different types of single bit cell soft failures, then discuss the two electrical nano-probing methods for the SRAM single bit cell soft failure.
Abstract The efficiency of Gas-Assisted Etching (GAE) and depositions performed using the Focused Ion Beam (FIB) technique is subject to numerous factors. Besides the wellknown primary parameters recommended by the FIB manufacturer (pixel spacing, dwell time, and gas pressures), certain secondary factors can also have a pronounced effect on the quality of these gas-assisted FIB operations. The position of the gas delivery nozzle during XeF2 mills on silicon is examined and was found to affect both the milling speed and the texture on the floor of the FIB trench. Limitations arising from the memory capacity of the FIB computer can also influence process times and trench quality. Exposing the FIB vacuum chamber to TMCTS during SiO2 depositions is found to temporarily impede the performance of subsequent tungsten depositions, especially following heavy or prolonged TMCTS exposure. A delay period may be required to achieve optimal tungsten depositions following TMCTS use. Finally, the focusing conditions of the ion beam are found to have a significant impact on the resistance of FIB-deposited metal films. This effect is attributed to partial milling of the deposition film due to the intense current density of the collimated ion beam. The resistances of metal depositions performed with intentionally defocused ion beams were found to be lower than those performed with focused beams.
Abstract Circuit level probing is testing, measuring, or characterizing the operation of an electronic circuit. It reveals the true operation of a circuit, and takes the next step beyond electrical engineering design and circuit simulation. This paper presents the return of circuit level probing in nanoelectronics by means of SEM based nanoprobing. It provides information on the process of characterizing resistance matching, diode matching, Op Amp offset matching, and mirrored current. Circuit level probing, using a SEM based nanoprober, identified the problem to be poor matching between the current mirror devices in the circuit. A family of curves device characterization was obtained from the circuit level probing. Discrete devices testing showed good correlation back to the circuit level data. The device mismatch was determined to be associated with the "as processed" built-in potential of the devices, with no abnormal influence from either the gate or drain electrical fields.
Abstract Failure analysis plays a very important role in semiconductor industry. Photon Emission Microscopy (PEM) has been extensively used in localization of fails in microelectronic devices. However, PEM emission site is not necessarily at the location of the defect. Thus, it has limitation for the success rate of the follow-up physical failure analysis focusing on the emission site. As semiconductor technology advanced in the 3D FinFET realm and feature size further shrank down, the invisible defects during SEM inspection are tremendously increased. It leads to the success rate further decreasing. To maintain good success rate of failure analysis for advanced 3D FinFET technology, electrical probing is necessary to be incorporated into the failure analysis flow. In this paper, first, the statistic results of PEM emission sites versus real defect locations from 102 modules of microprocessors manufactured by 14nm 3D FinFET technology was present. Then, we will present how to wisely design electrical probing plan after PEM analysis. The electrical probing plans are tailored to different scan chain and ATPG failures of microprocessors for improving failure analysis success rate without increasing too much turn-around time. Finally, two case studies have been described to demonstrate how the electrical probing results guide the follow-up physical failure analysis to find the defect.
Abstract FIB techniques have provided a means for the nanometer-scale spatially confined etching and deposition processes required during repair or editing of advanced integrated circuit (IC) prototypes and lithographic masks. Primary sample properties that can lead to limitations on the applicability of FIB for IC repair are the material composition, aspect ratio, and feature packing density. The typical aims when developing a gas-assisted-etch (GAE) process for IC repair applications are enhancement of etch rate, increased volatilization of reaction products, and improved material selectivity. This paper presents results from a novel two-step process for clearing large areas of one micron thick (upper-level metal) layers. Better equalization of etch rates was achieved using the novel developed FIB GAE process. The paper describes the preliminary results obtained using non-gallium-ion beam based approaches for controlled surface modification during the editing of IC repair samples.
Abstract This paper describes novel concepts in equipment and measurement techniques that integrate optical electrical microscopy and scanning probe microscopy (SPM) capabilities into a single tool under the umbrella of optical nanoprobe electrical (ONE) microscopy. Optical imaging ONE microscopy permits non-destructive measurement capability that was lost more than a decade ago, when the early metal levels became electrically inaccessible to microprobers. SPM imaging techniques do not have sensitivity to many types of defects, and nanoprobing all of the transistors in an area pinpointed by optical electrical microscopy is often impractical. Thus, in many cases, ONE microscopy capability will permit analytical success instead of failure.
