We have studied in detail the effects of nitrogen implantation into a p + polysilicon gate on gate oxide properties for the surface p-channel metal oxide semiconductor (PMOS) below 0.25 µm. The nitrided oxide film can be easily formed by the pile-up of nitrogen into the gate oxide film from the polysilicon gate. It was found that boron penetration through the gate oxide film can be effectively suppressed by nitrogen implantation into a p + polysilicon gate because nitrogen in the polysilicon film can suppress boron diffusion, and the nitrided oxide film can also act as a barrier to boron diffusion. Moreover the hot-carrier hardness can be remarkably improved by the nitrided oxide film since interface state generation can be suppressed by the nitrided oxide film. Furthermore the number of electron traps in the gate oxide film can also be reduced by nitrogen implantation.
Vertical injection logic (VIL) is a novel form of integrated injection logic (I/SUP 2/L). A vertical p-n-p transistor is used in place of a lateral p-n-p transistor to obtain an improved performance at the same packing density as conventional I/SUP 2/L. The current gain of the p-n-p transistor can be increased, which leads to the excellent power-delay product. The intrinsic delay time is also improved by the action of the bottom injector as a hole sink. The fabrication process and electrical characteristics of VIL are described and contrasted with conventional I/SUP 2/L. A tentative hole sink model is also proposed. The experimental results showed the minimum delay time of 8.8 ns and the power-delay product of 0.07 pJ at low power level below 1 /spl mu/W for VIL compared to 25 ns and 0.18 pJ for standard I/SUP 2/L.
A concept was presented for the prediction of the device lifetimes for the hot-carrier effect (hot-carrier lifetimes) in floating SOI MOSFETs. The concept is that hot-carrier lifetimes in floating SOI MOSFETs can be predicted by estimating the hole current. In order to verify the validity of this concept, the hole current was investigated using device simulation. The results showed that the ratio of the hole current to the drain current in a floating-body SOI MOSFET is approximately equal to the ratio of substrate current to drain current in a body-tied one. Based on this fact, a method for accurately predicting the hot-carrier lifetime in floating-body SOI MOSFETs was proposed. The hot-carrier lifetime predicted with this method agreed well with the experimental results. This study showed that only the drain current difference between floating and body-tied structures results in lifetime differences, and there is no special effect on hot-carrier degradation in floating SOI MOSFETs. In this prediction, therefore, floating SOI MOSFETs can be treated in the same way as bulk MOSFETs. Hot-carrier lifetimes in floating SOI MOSFETs can be predicted using the hole current, while substrate currents are used in bulk MOSFETs.
1996 International Conference on Solid State Devices and Materials,Analysis of the Charge Density at Field Oxide/SOI and SOI/Buried Oxide Interfaces in Partially Depleted SOI MOSFET's with and without Hydrogenation
The combination of FAMOS and CMOS processes produces a new PROM with high performance and low power. This combined process named FA-CMOS will be described. The FA-CMOS process is based on the conventional silicon gate CMOS process using the selective oxidation process (SOP) technology. It is necessary to form the avalanche injection region capable of programming with low voltage without the breakdown of N + P - junction ( N + diffusion to P - well region ). Arsenic ions are implanted to form this region and the avalanche injection voltages of less than 20 V are obtained. In addition to the above mentioned process, the double diffusion technology simplifies the formation of source-drain and isolation region. Extremely low power ( 0.6 µW/bit ) PROM was successfully fabricated using the FA-CMOS process.
Electron capture and excess current after substrate hot‐hole injection into 60 and 131 Å silicon dioxides have been studied. After the hole injection into 131 Å oxides, a transient excess current appears in the gate current‐oxide field characteristics and electrons are captured even at low oxide fields for the positive gate polarity. The low field electron capture is explained based on the tunneling of electrons from the substrate into the positive charge and neutral trap centers created near the substrate‐ interface. The transient excess current is suggested to be due to the two current components: the displacement current component due to the electron capture by both the positive charge and the neutral trap centers, and the tunneling current component enhanced by the positive charge located near the interface. In 60 Å oxides, excess currents appear for both positive and negative gate polarities after the hole injection, and consist of the steady‐state leakage current component and the transient current component. The leakage current induced by the hole injection is increased as the oxide thickness is decreased.
This paper describes the implementation of a BIST circuit with timing margin test functions to a 200 MHz 1 Gbit synchronous DRAM. 220 ps-resolution timing signals with up to 80 ns cycle time are generated by a phase-locked loop (PLL) circuit and a delayed timing generator. These timing signals are used not only as actual control signals but also as reference signals in an AC timing comparator. The entire BIST circuit, which includes 20/spl times/4 bit LFSRs, occupies only 0.8% of the chip area. A cost evaluation of the BIST shows that the technology is effective for 64 Mbit high-speed DRAMs and beyond.
This paper describes key techniques for a 1.6-GB/s high data-rate 1-Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are targeted to the advanced unified memory system in which a single DRAM (array) is used as both the main memory and the three-dimensional (3-D) graphics frame memory in a time sharing fashion. The 200-MHz high-speed operation is achieved by the unique hierarchical square-shaped memory block (SSMB) layout and the novel distributed bank (D-BANK) architecture. A 0.29 /spl mu/m/sup 2/ cell and 581.8 mm/sup 2/ small die area are achieved using 0.15-/spl mu/m CMOS technology. The /spl times/61 chip uses 196-pin BGA type chip-scale-package (CSP). Implementation of a built-in self-test (BIST) circuit with a margin test capability is also described.
