Systems-on-Chip (SoC) and Systems-on-Package (SoP) are becoming more and more heterogeneous systems. In order to validate systems containing such a variety of components, global multi-domain simulation of different aspects becomes especially important. Hardware/software, analog/digital, and electronic/mechanical/optic mixed simulations must be accessible. This paper presents a methodology to establish an environment for the global modeling and simulation of system-on-chip embedding MEMS devices. This methodology is illustrated in two co-simulation frameworks: the optical cross-connect co-simulation framework and the electro-thermal co-simulation framework.
The present work has shown that a citrus leaf can support the nutritive needs of 5 individual P. citrella. Beyond this number of feeding larvae leaf mortality results as larval densities increase. An increasing number of female P. citrella (> 6 females per suitable leaf) adversely affects rearing due to competition for oviposition sites and resource limitation for developing larvae. To maximize efficient production of P. citrella, a quantitative relationship between ovipositing females, larval densities, and leaf quality needs to be determined. Our results indicate that one ovipositing female should have access to six leaves under rearing conditions. INTRODUCTION To control exotic pests, classical biological control attempts to seek in the pest’s original country its natural enemies (e.g., the case of Aleurothrixus floccosus) for release in the invaded territory. Classical biological control has been used for citrus leafminer in different countries that have been recently invaded over the period 1993-1995 (Heppner, 1993; Beattie and Smith 1993; Garijo and Garcia, 1994; Anagnou-veroniki, 1995; Berkani, 1995; Ortu and al., 1995; Argov and Rossler, 1996; Aytas and al., 1996; Jerraya et al., 1996). One major difficulty has been the mass rearing of leafminers to supply to parasitoids being used in the biological control program. To maximise rearing efficiency we have investigated the precise conditions needed for maximum leafminer multiplication to mass rear parasitoids for of augmentative releases. MATERIALS AND METHODS One hundred two year old plants (Poncirus trifoliata), maintained in greenhouses were selected for rearing studies, pinched, and isolated in one of three cages (A, B, and C). These plants were carefully looked after and subjected to fertigation and pinching to promote healthy continuous growth. Seventeen days after pinching, grown leaves become suitable for oviposition by P. citrella. When P. citrella was released into cages with plants there were approximately 500 leaves/cage for females. We introduced 40, 80 and 160 couples respectively in cages A, B and C on June 11, 2002. These cages were kept inside an experimental greenhouse where temperature and humidity were controlled (average temperature 30°C and RH 80-90 %) (after Smith and Hoy, 1995). One week after inoculation the first batch of oviposition occurred and we focused on % of mortality, rate of infestation, rate of eclosion, number of eggs, of larvae and of pupae in each cage. This was followed a second set of observations done one week later (i.e., 15 days post-inoculation on June 25 2002). Statistical analyses were done using (SAS, 2000). RESULTS AND DISCUSSION P. citrella offspring 7 days after inoculation – Table 1 We found that: 1) The rate of P. citrella eclosion was the same whatever the cage density. This means that the activity of laying starts almost in a simultaneous manner for all the females and that the duration of incubation was comparable across the three cages stocked with different densities of ovipositing females. 2) The absence of the third instar larva in the three cages shows either there is a delay in oviposition or that the conditions of the cages were not favourable for rearing as under optimal conditions, the duration of the egg stage and first instar larva (L1) are 2 days and 1 day, respectively. 3) If the density of initial inoculation affects the rate of female oviposition in cages, we can say that this capacity is about 97 % in the cage A, 73% in the cage B, and declines to 59 % in the cage C. This suggests that increasing the density of ovipositing females in cages adversely affects oviposition rates. 4) Numbers of eggs laid per leaf were 5, 9, 18 in the cages A, B and C, respectively. Consequently survivorship rates of first and second instar larvae were affected, most likely a result of overpopulation and resource depletion which resulted in mortality rates of 6%, 65% and 79% for cages A, B and C, respectively. Oviposition deterring pheromones applied to leaves on which have freshly deposited eggs do not deter further oviposition by females under crowded conditions. 5) P. citrella has a male:female sex ratio of 1:1. Therefore, we can estimate that the number of females produced per cages was 40 in cage A, 80 in cage B and 160 in cage C. These female populations, laid 2470 eggs (494 x 500), 4720 (944 x 500) and 8975 eggs (1795 x 500) in cages A, B, and C, respectively. In this way, we calculated the fecundity per female per cage as 61 for cage A, 59 for cage B, and 56 for the cage C. The differences between the fecundity values were not significant and were similar to values considered as being around the average fecundity for female P. citrella.
In this paper we discuss the generation of reprogrammable controllers. This generation is performed by the use of an existing high-level synthesis environment initially intended to hardwired circuits. Starting from a high-level behavioral specification (in algorithmic form) describing the function of the circuit, the high-level synthesis provides an architecture composed of a data-path and a controller. The generated architecture is flexible due to the use of a controller based on a ROM (reprogrammable). This paper describes an initial set of modifications to an architectural synthesis system targeting the generation of programmable controllers. The designer can then generate both style of architecture, hardwired and programmable, using the same synthesis system and can quickly evaluate the trade-offs of hardware decisions.
La conjonction de l'evolution des technologies de fabrication des circuits integres et de la nature du marche des systemes electroniques fait que l'on est amene a concevoir des circuits de plus en plus complexes (plusieurs millions) de transistors en un temps de plus en plus court (quelques mois). Ce phenomene a entraine une metamorphose du processus de conception. Si le principe de la conception reste le meme (il s'agit de generer une realisation physique sous forme d'une puce en partant d'une specification systeme), les outils mis en œuvre et l'organisation du travail durant le processus de conception ont, en revanche, beaucoup evolue. Ainsi, on est passe de la conception ou l'on dessinait les masques du circuit sur du papier special, a une conception quasi automatique qui part d'une description du comportement du circuit sous forme d'un programme dans un langage de haut niveau. Cet ouvrage a pour but de decrire les methodes et les outils d'aide a la conception logique et physique des systemes electroniques digitaux integres. Le chapitre 2 presente les fondements de la synthese de circuits logiques a partir de modeles ecrits dans des langages de description de materiel (VHDL / Verilog). Le lecteur aura ainsi les connaissances necessaires pour devenir un utilisateur averti des outils de synthese logique et un concepteur-programmeur. Le chapitre suivant est consacre a la conception physique, l'etape ultime dans une chaine de conception de circuits integres, celle de l'implementation en vue de l'obtention des dessins de masques servant a la fabrication du circuit integre. Ses principales methodologies (placement et routage automatiques, synthese automatique d'arbre d'horloge, etc.) seront donc decrites ainsi que les differentes etapes de la verification physique (extraction des composants parasites, etc.). L'accroissement en complexite des circuits integres et la necessite croissante de reduire les temps de mise sur le marche exigent la mise en place d'une strategie de test de la qualite du produit fini. Le chapitre 4 traite du test des circuits en decrivant les concepts et les outils necessaires a la mise en place d'une telle strategie. Le concept de communication asynchrone, tres en vogue en ce moment, repose sur le concept de decouplage des differents modules constituant un systeme. Ce principe, qui est a la base de toutes les approches modulaires developpees pour maitriser la complexite, peut amener des solutions plus efficaces en termes de performance et de consommation. Les concepts qui regissent le fonctionnement et l'implementation des circuits asynchrones sont presentes dans le chapitre 5 ainsi que les formalismes et les methodes utilises pour la synthese de circuits asynchrones. En conclusion, le lecteur trouvera une liste des principaux outils de CAO de circuits et systemes existants. Le chapitre 6 passe en revue quelques outils du commerce s'integrant dans le flot de conception des circuits et systemes, en mettant l'accent en particulier sur les outils et les nouvelles methodes de conception a base d'IP (composants virtuels ou «propriete intellectuelle».
This paper presents an approach for abstract modeling of the functional behavior of hardware architectures using Hierarchical Colored Petri Nets (HCPNs). Using HCPNs as architectural models has several advantages such as higher estimation accuracy, higher flexibility, and the need for only one estimation tool. This makes the approach very useful for designing component models used for performance estimation in Hardware/Software Codesign frameworks such as the LYCOS system [14]. The paper presents the methodology and rules for designing component models using HCPNs. Two examples of architectural models are presented, namely a model of the DLX pipeline processor [9], and a model of a fixed point unit used in the AMICAL system [13]. The methodology presented in this paper is a pragmatic example of the usefulness of HCPNs. The focus is not on the theoretical aspects of Petri Nets but on the application of the Petri Net methodology in an existing Codesign environment.
The SYCO system is a silicon compiler for VLSI ASICs specified by algorithms. SYCO starts from an algorithmic description and produces a circuit that realises the algorithm. Although SYCO starts from a high-level hardware description language, the translation scheme from algorithmic description to layout is easy to understand, and there is a correspondence between the input description and the layout. Consequently the designer may easily modify the input description in order to force the compiler to produce a given result.
