Abstract This study aims at developing an optimization framework for electric vehicle charging by considering different trade-offs between battery degradation and charging time. For the first time, the application of practical limitations on charging and cooling power is considered along with more detailed health models. Lithium iron phosphate battery is used as a case study to demonstrate the effectiveness of the proposed optimization framework. A coupled electro-thermal equivalent circuit model is used along with two battery health models to mathematically obtain optimal charging current profiles by considering stress factors of state-of-charge, charging rate, temperature and time. The optimization results demonstrate an improvement over the benchmark constant current–constant voltage (CCCV) charging protocol when considering both the charging time and battery health. A main difference between the optimal and the CCCV charging protocols is found to be an additional ability to apply constraints and adapt to initial conditions in the proposed optimal charging protocol. In a case study, for example, the ‘optimal time’ charging is found to take 12 min while the ‘optimal health’ charging profile suggests around 100 min for charging the battery from 25 to 75% state-of-charge. Any other trade-off between those two extreme cases is achievable using the proposed charging protocol as well.
The authors explore the potential for enhanced performance in asynchronous pipeline control, by eliminating unneccessary signalling in bounded-delay asynchronous systems. An improvement of 15 and 36% in cycle time over optimal two and four phase asynchronous dynamic logic implementations, respectively, is demonstrated.
A combining cavity for RF power sources has been investigated as a way of saving space, in comparison to waveguides, and as a way of combining power with graceful degradation if one or more component were to fail. The cavity has been investigated as the maximum power output of an Inductive Output Tube (IOT) for CW is 80KW at 500MHz and a proposed output of 20KW at 1.3GHz and most RF systems for particle accelerators require much more than this. Although 1.3GHz klystrons do exist they are vastly more expensive to purchase and maintain. Also the down time could be minimised to minutes in the even of a single IOT failure where as a klystron has a minimum downtime of several days in the event of a failure. Initially the cavity and its inputs were simulated in CSTs’ Microwave studio. After optimising the cavity to ensure the minimum reflection at the input ports and maximum transmission at the output port, a low power model was then created from aluminium. Signal generators were used to power the model and a network analyser was used to check the output. The model was used to compare the results gained from the computer simulation and to obtain results from asymmetric positioning of the ports, which was not possible in the simulation.
We explore the potential for enhanced performance in asynchronous pipelines by the elimination of unnecessary signalling from the critical path, thus making the common case fast. An improvement of 15% over an optimal two-phase signalling approach for both static and dynamic logic control is demonstrated. We describe extensions to the approach that add functionality with no cycle time overhead.
In this paper the potential speed and power efficiency of two-phase asynchronous systems operating under a bounded-delay model are explored. It is shown that two-phase bounded-delay systems can significantly outperform four-phase approaches published to date. The design of a prototype microprocessor using this two-phase approach is then described, and preliminary results are presented.
This paper describes the design of a FFT chip, up to eight of which may be cascaded together to produce continuous streams of transforms of up to 65536 points. The control structure is asynchronous, and hence a fast, very low power, slew-free environment is provided. Aspects of the event controlled methodology used for this, and other designs, is also presented.
This paper introduces some of the principal design issues encountered in the development of a prototype asynchronous microprocessor using a two-phase communication strategy. These issues include the control of the processor pipeline, register tagging, branch techniques, and the implementation of caches. The arbitration and synchronisation methods employed in the design are discussed, and expected performance figures based on block simulation results are given.
'/%3e%3c/defs%3e%3cpath fill='%23012169' d='M0 0h10080v5040H0z'/%3e%3cpath stroke='%23fff' stroke-width='.6' d='m0 0 6 3m0-3L0 3' clip-path='url(%23b)' transform='scale(840)'/%3e%3cpath stroke='%23e4002b' stroke-width='.4' d='m0 0 6 3m0-3L0 3' clip-path='url(%23c)' transform='scale(840)'/%3e%3cpath stroke='%23fff' stroke-width='840' d='M2520 0v2520M0 1260h5040'/%3e%3cpath stroke='%23e4002b' stroke-width='504' d='M2520 0v2520M0 1260h5040'/%3e%3cg fill='%23fff'%3e%3cuse xlink:href='%23d' x='2520' y='3780'/%3e%3cuse xlink:href='%23a' x='7560' y='4200'/%3e%3cuse xlink:href='%23a' x='6300' y='2205'/%3e%3cuse xlink:href='%23a' x='7560' y='840'/%3e%3cuse xlink:href='%23a' x='8680' y='1869'/%3e%3cuse xlink:href='%23e' x='8064' y='2730'/%3e%3c/g%3e%3c/svg%3e)
'%3e%3cpath fill='%23012169' d='M0 0v30h60V0z'/%3e%3cpath stroke='%23fff' stroke-width='6' d='m0 0 60 30m0-30L0 30'/%3e%3cpath stroke='%23C8102E' stroke-width='4' d='m0 0 60 30m0-30L0 30' clip-path='url(%23b)'/%3e%3cpath stroke='%23fff' stroke-width='10' d='M30 0v30M0 15h60'/%3e%3cpath stroke='%23C8102E' stroke-width='6' d='M30 0v30M0 15h60'/%3e%3c/g%3e%3c/svg%3e)
