Abstract Since strain engineering plays a key role in semiconductor technology development, a reliable and reproducible technique to measure local strain in devices is necessary for process development and failure analysis. In this paper, geometric phase analysis of high angle annular dark field - scanning transmission electron microscope images is presented as an effective technique to measure local strains in the current node of Si based transistors.
Stacking fault formation during epitaxial SiGe layer growth in bipolar complementary metal oxide semiconductor (BiCMOS) process which caused high yield loss due to its leakage current on bipolar transistors has been studied. Through the analysis of process flow, oxidation induced stacking faults were indicated as a possible root cause of the yield loss. The identification of the oxidation induced stacking fault mechanism and understanding of its process dependency are very critical to improve the yield and obtain fast ramp-up. This paper includes the comprehensive characterization of oxidation induced stacking fault mechanisms in SiGe-based BiCMOS devices. Figure 1 is a typical cross-sectional view of the bipolar transistor studied and its strain map by geometric phase analysis, which shows that ~1GPa compressive stress exists in the SiGe layer due to lattice constant mismatch of SiGe and Si. Since such high stress fields are formed in the film, a small amount of addition stress field can easily induce crystal defect. When oxygen atoms are supersaturated in the epitaxial process, the additional stress field is formed because supersaturated oxygen atoms are agglomerated as interstitials in the film. [1, 2] After electrical isolations of leakage locations in failing devices, actual root cause of the failure was verified as shown in Figure 2 (a). Figure 2 (a) shows that stacking fault grew along the (111) slip plane of Si and a single line of dislocation was formed at tip of the stacking fault, which caused leakage current on the bipolar transistor. To find the mechanism of stacking fault formation, in-line SEM inspection was performed right after SiGe epitaxial growth process. Through the isolation of stacking fault by the in-line SEM, follow-up TEM analysis on one of stacking faults shows that stacking fault starts from the epitaxial Si seed layer just below SiGe layer as shown in Figure 2 (b). Any introduction of oxygen during Si seed layer formation can create stress by saturated oxygen atoms and this additional stress can be added up with the mismatch strain between SiGe and Si, which caused crystal defect such as stacking fault. This result correlates with the analysis of oxygen concentration in epitaxial growth tool. Stained SEM images of the stacking faults with diluted Schimmel (8g CrO3, 250ml DI H2O and 200ml 49% HF) also helps to understand the whole structure of stacking fault defect as shown in Figure 3. This study presented TEM and SEM microscopic analysis of stacking fault formation during epitaxial SiGe process on BiCOM devices. Oxygen was introduced into epitaxial growth chamber during the process, and the oxygen caused stacking fault formation, and then this defect became a leakage path during device operation. This oxidation induced stacking fault defect formation can be minimized by preventing any introduction of oxygen during epitaxial SiGe process and in-line SEM inspection.
This letter reports that geometric phase analysis of high-resolution images acquired in the high-angle annular darkfield scanning transmission electron microscopy can map strains at levels of accuracy and reproducibility needed for strained-silicon-device development. Two-dimensional strain maps were reconstructed for a p-type metal-oxide-semiconductor device which was strain-engineered using a recessed source and drain. This metrology provides sufficiently practical and reproducible local-strain tensors which can be measured on a routine basis. The techniques demonstrated here are informative for process development and failure analysis in the semiconductor industry.
Phase profiles within core-shell nanowires composed of intrinsic germanium cores and shells of germanium oxide and/or doped germanium were imaged using electron holography in a transmission electron microscope. Accurate mean inner potentials for germanium and its oxide were determined from phase data obtained from experimental electron holography with knowledge of the thickness profile of the nanowire. Using measured and simulated phase profiles, it was possible to determine the dopant concentration within a shell of doped germanium around an intrinsic germanium core. Measurement of mean inner potentials and dopant levels within semiconductor core-shell nanowires was demonstrated.
The current flow through interconnects can be locally crowded and its impact on electromigration (EM) has not been studied well. We design test structures with different levels of current crowding and test its impact on EM Lifetime. We also simulate the current crowding of each case and correlate them with the observed EM lifetimes. Even if there is localized hot spot having very high current density but the region is small, the impact on EM lifetime is small. For example, EM lifetime decreases less than 4% for 24% local current density increase. The extent of impact is a function of length of the crowding as well as the local current density. Including both the current density and the length effects on EM, we propose a quantifiable local current crowding factor (LCCF). The EM lifetime depends on the power of the LCCF with variable power exponents. The power exponent increases with LCCF and reaches a maximum value before starting to decrease to zero. At very large LCCF, when currents are crowded over long length, the impact is not localized anymore and the additional lifetime reduction by additional current crowded space is zero. So the power exponent is zero for the case. Utilizing the LCCF provides a practical method for how to address the inevitable local current crowding and enhance the EM check accuracy especially for the analog semiconductor circuits.
Semiconductor interface investigation via analytical characterization represents a major focus for Failure Analysis and Process Characterization Teams. Investigation can be performed via destructive techniques through depth profiling until reaching the interface while collecting matrix and impurity distributions as a function of depth and also via nondestructive techniques which preserves information about the interface. Interface characterization involves the deployment of Failure Analysis resources, employing advance imaging and materials characterization techniques like TEM (transmission electron microscopy), SEM (Scanning Electron Microscopy), DSIMS (dynamic secondary mass spectrometry), TOFSIMS (time of flight secondary ion mass spectrometry), Auger, XRF (X-Ray Fluorescence), and XPS (X-ray Photoelectron Spectroscopy). As first exampled in the case study detailed in this paper, increased aluminum resistance was caused by oxidation of aluminum metal while in a cooling chamber prior to barrier layer deposition due to chamber lid atmospheric leaks. High resistivity interconnect issues can be related to interface quality and diminish product performance up to complete failure. Typical methods like cross section analysis via TEM and SEM did not reveal any abnormality. This prompted further investigation where innovative depth profiling methods of DSIMS / TOFSIMS to the encapsulated interface was used, highlighting the presence of oxidized aluminum metal. In another example, analysis was performed nondestructively utilizing a newly developed High Energy HAXPS mode, allowing for the successful characterization of interfaces and high electron mobility transistors where layer interaction is vital.
The distribution of breakdown times of thin film dielectrics, stressed in a constant voltage mode, is generally interpreted in terms of percolation theory of dielectric breakdown. The percolation model suggests that relative distribution of failure times (normalized to the mean) should narrow down considerably for thicker dielectrics. Explicitly contradicting this prediction, we find a larger distribution of failure times even for relatively thick polycrystalline oxides. We use atomic force microscopy and conductive AFM measurements to confirm that breakdown in these films are primarily localized in the grain boundaries, decorated with large number of pre-existing defects. The classical percolation model—adapted to this specific situation of spatially localized trap generation—offers an intuitive explanation of the breadth of the failure time distribution in thick polycrystalline dielectric. The theory offers an opportunity to optimize the intrinsic trade-off between variability and reliability in polycrystalline films.
The effects of Ta barrier thickness on electromigration reliability of dual-damascene Cu/porous methylsilsesquioxane interconnects were investigated. With decreasing Ta barrier thicknesses, the threshold product of current density and line length (jL)c was found to be reduced due to less structural confinement from thinner barriers. The effect can be accounted for by the effective modulus of the structure except for the 75-Å Ta barrier where the (jL)c product is reduced more than expected, probably due to the presence of defects in the barrier. Results from the early failure test structures revealed a bimodal failure distribution for samples with the 75-Å and l00-Å barriers. Focused ion beam microprobe and transmission electron microscopy observations revealed that the weak-mode early failure was caused by Cu outdiffusion through structural defects in the thin Ta barrier.
