Yu-Pei Liang

National Chung Cheng University

Author Statistics

Papers

Citation

H-Index

i-10 index

Research Trends

Author Order

Document Type

Co-Authors

Wei‐Kuan Shih

National Tsing Hua University

Shuo-Han Chen

National Yang Ming Chiao Tung University

Yuan-Hao Chang

Institute of Information Science, Academia Sinica

Tseng‐Yi Chen

National Central University

Hsin‐Wen Wei

Tamkang University

Ching-Che Chung

National Chung Cheng University

Yen-Ting Chen

National Central University

Heng‐Yin Chen

Industrial Technology Research Institute

Yi-Han Lien

National Tsing Hua University

I-Ju Wang

National Tsing Hua University

Cooperative Institutions

National Tsing Hua University

National Yang Ming Chiao Tung University

Institute of Information Science, Academia Sinica

National Chung Cheng University

National Taiwan University

National Taipei University of Technology

National Central University

Academia Sinica

National Cheng Kung University

Tamkang University

Author Statistics

Papers

Citation

H-Index

i-10 index

Research Field

Implementation of Lightweight Convolutional Neural Networks with an Early Exit Mechanism Utilizing 40 nm CMOS Process for Fire Detection in Unmanned Aerial Vehicles

Sensors (2024)

Yu-Pei Liang Chen‐Ming Chang Ching-Che Chung

The advancement of unmanned aerial vehicles (UAVs) enables early detection of numerous disasters. Efforts have been made to automate the monitoring of data from UAVs, with machine learning methods recently attracting significant interest. These solutions often face challenges with high computational costs and energy usage. Conventionally, data from UAVs are processed using cloud computing, where they are sent to the cloud for analysis. However, this method might not meet the real-time needs of disaster relief scenarios. In contrast, edge computing provides real-time processing at the site but still struggles with computational and energy efficiency issues. To overcome these obstacles and enhance resource utilization, this paper presents a convolutional neural network (CNN) model with an early exit mechanism designed for fire detection in UAVs. This model is implemented using TSMC 40 nm CMOS technology, which aids in hardware acceleration. Notably, the neural network has a modest parameter count of 11.2 k. In the hardware computation part, the CNN circuit completes fire detection in approximately 230,000 cycles. Power-gating techniques are also used to turn off inactive memory, contributing to reduced power consumption. The experimental results show that this neural network reaches a maximum accuracy of 81.49% in the hardware implementation stage. After automatic layout and routing, the CNN hardware accelerator can operate at 300 MHz, consuming 117 mW of power.

10.3390/s24072265

Cite

Citations (2)

On Minimizing the Read Latency of Flash Memory to Preserve Inter-Tree Locality in Random Forest

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design (2022)

Yu‐Cheng Lin Yu-Pei Liang Tseng‐Yi Chen Yuan-Hao Chang Shuo-Han Chen

Many prior research works have been widely discussed how to bring machine learning algorithms to embedded systems. Because of resource constraints, embedded platforms for machine learning applications play the role of a predictor. That is, an inference model will be constructed on a personal computer or a server platform, and then integrated into embedded systems for just-in-time inference. With the consideration of the limited main memory space in embedded systems, an important problem for embedded machine learning systems is how to efficiently move inference model between the main memory and a secondary storage (e.g., flash memory). For tackling this problem, we need to consider how to preserve the locality inside the inference model during model construction. Therefore, we have proposed a solution, namely locality-aware random forest (LaRF), to preserve the inter-locality of all decision trees within a random forest model during the model construction process. Owing to the locality preservation, LaRF can improve the read latency by 81.5% at least, compared to the original random forest library.

Locality of reference

10.1145/3508352.3549365

Cite

Citations (0)

A Multiplier-Free Convolution Neural Network Hardware Accelerator for Real-Time Bearing Condition Detection of CNC Machinery

Sensors (2023)

Yu-Pei Liang Ming-You Hung Ching-Che Chung

In various industrial domains, machinery plays a pivotal role, with bearing failure standing out as the most prevalent cause of malfunction, contributing to approximately 41% to 44% of all operational breakdowns. To address this issue, this research employs a lightweight neural network, boasting a mere 8.69 K parameters, tailored for implementation on an FPGA (field-programmable gate array). By integrating an incremental network quantization approach and fixed-point operation techniques, substantial memory savings amounting to 63.49% are realized compared to conventional 32-bit floating-point operations. Moreover, when executed on an FPGA, this work facilitates real-time bearing condition detection at an impressive rate of 48,000 samples per second while operating on a minimal power budget of just 342 mW. Remarkably, this system achieves an accuracy level of 95.12%, showcasing its effectiveness in predictive maintenance and the prevention of costly machinery failures.

Gate array

10.3390/s23239437

Cite

Citations (0)

Facilitate External Sorting for Large-Scale Storage on Shingled Magnetic Recording Drives

Lecture notes in networks and systems (2019)

Yu-Pei Liang Min-Hong Shen Yi-Han Lien Wei‐Kuan Shih

Merge (version control)

Auxiliary memory

10.1007/978-3-030-12385-7_80

Cite

Citations (0)

Selective Data Protection for Energy-Efficient Deep Neural Network Inference in Intermittent IoT Systems

J.C. Liu Yu-Pei Liang

Intermittent computing systems allow devices to operate under unstable and weak power conditions. When a device performing long tasks is interrupted due to power instability, a checkpoint mechanism is used to save data to non-volatile memory before the system shuts down, allowing computation to resume when power is restored. However, power failures can leave data stored in nonvolatile memory vulnerable to tampering during the downtime. To address this, recent research has proposed encrypting and verifying data to protect it and prevent replay attacks that could disrupt program execution and deep inference sequences.

Deep Neural Networks

10.1145/3698384.3699618

Cite

Citations (0)

SACS: A Self-Adaptive Checkpointing Strategy for Microkernel-Based Intermittent Systems

Yen‐Ting Chen Han-Xiang Liu Yuan-Hao Chang Yu-Pei Liang Wei‐Kuan Shih

Intermittent systems are usually energy-harvesting embedded systems that harvest energy from ambient environment and perform computation intermittently. Due to the unreliable power, these intermittent systems typically adopt different checkpointing strategies for ensuring the data consistency and execution progress after the systems are resumed from unpredictable power failures. Existing checkpointing strategies are usually suitable for bare-metal intermittent systems with short run time. Due to the improvement of energy-harvesting techniques, intermittent systems are having longer run time and better computation power, so that more and more intermittent systems tend to function with a microkernel for handling more/multiple tasks at the same time. However, existing checkpointing strategies were not designed for (or aware of) such microkernel-based intermittent systems that support the running of multiple tasks, and thus have poor performance on preserving the execution progress. To tackle this issue, we propose a design, called self-adaptive checkpointing strategy (SACS), tailored for microkernel-based intermittent systems. By leveraging the time-slicing scheduler, the proposed design dynamically adjust the checkpointing interval at both run time and reboot time, so as to improve the system performance by achieving a good balance between the execution progress and the number of performed checkpoints. A series of experiments was conducted based on a development board of Texas Instrument (TI) with well-known benchmarks. Compared to the state-of-the-art designs, experiment results show that our design could reduce the execution time by at least 46.8% under different conditions of ambient environment while maintaining the number of performed checkpoints in an acceptable scale.

Microkernel

10.1145/3531437.3539705

Cite

Citations (0)

CNN Hardware Accelerator for Real-Time Bearing Fault Diagnosis

Sensors (2023)

Ching-Che Chung Yu-Pei Liang Jiang HongJin

This paper introduces a one-dimensional convolutional neural network (CNN) hardware accelerator. It is crafted to conduct real-time assessments of bearing conditions using economical hardware components, implemented on a field-programmable gate array evaluation platform, negating the necessity to transfer data to a cloud-based server. The adoption of the down-sampling technique augments the visible time span of the signal in an image, thereby enhancing the accuracy of the bearing condition diagnosis. Furthermore, the proposed method of quaternary quantization enhances precision and shrinks the memory demand for the neural network model by an impressive 89%. Provided that the current signal data sampling rate stands at 64 K samples/s, the proposed design can accomplish real-time fault diagnosis at a clock frequency of 100 MHz. Impressively, the response duration of the proposed CNN hardware system is a mere 0.28 s, with the fault diagnosis precision reaching a remarkable 96.37%.

SIGNAL (programming language)

10.3390/s23135897

Cite

Citations (4)

B*-Sort: Enabling Write-Once Sorting for Nonvolatile Memory

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2020)

Yu-Pei Liang Tseng‐Yi Chen Yuan-Hao Chang Shuo-Han Chen Hsin‐Wen Wei

Nonvolatile random access memory (NVRAM) has been regarding a promising technology to replace DRAM as the main memory in embedded systems owing to its nonvolatility and low idle power consumption. However, due to the asymmetric read/write costs and limited lifetime of NVRAM, most of the existing fundamental algorithms are not NVRAM-friendly with their write pattern and write intensiveness. Thus, existing fundamental algorithms for NVRAM embedded devices has been revealed. For instance, as the sorting algorithm is one of the most fundamental algorithms, most of the existing sorting algorithms are not NVRAM-friendly because they impose heavy write traffic [i.e., O(n lgn)] on main memory, where n is the number of unsorted elements. To resolve this issue, this article proposes a write-once sorting algorithm, namely B*-sort, to reduce the amount of write traffic on NVRAM-based main memory. B*sort adopts a brand-new concept, i.e., tree-based sort, inspired by the binary-search-tree structure to achieve the write-once property which can guarantee the optimal endurance during the sorting process. According to the experimental results, B*-sort can achieve significant performance improvement for sorting on NVRAM-based systems.

Non-Volatile Memory

10.1109/tcad.2020.2979819

Cite

Citations (13)

Exploring Skyrmion Racetrack Memory for High Performance Full-Nonvolatile FTL

Ya-Hui Yang Yu-Pei Liang Cheng-Hsiang Tseng Shuo-Han Chen

Skyrmion racetrack memory (SK-RM) has shown great potential for replacing DRAM or SRAM with its high density and great access performance. Unlike other non-volatile random access memory (NVRAM), SK-RM supports random updates through injecting or removing skyrmions on a racetrack. Injected skyrmions can be shifted along the racetrack to store data. Nevertheless, since most previous studies focus on minimizing the number of inject or shift operations, the unique feature of moving skyrmions vertically between racetracks and the possibility of utilizing free or invalid memory space to preserve skyrmions receive much less attention. In this paper, we observe that vertical movement and preservation of skyrmions provide a great opportunity to mitigate the possible run time performance degradation issue of NVRAM-based flash translation layer (FTL), as writes of mapping entries typically induce more overhead than reads on NVRAM. To fully exploit the benefits of SK-RM within the FTL mechanism, this paper proposes an SK-FTL to enable a high-performance and non-volatile FTL by preserving and reforming skyrmions over multiple data writes. Experimental results suggest that SK-FTL can effectively improve the performance of non-volatile FTL.

Skyrmion

Racetrack memory

Non-volatile random-access memory

Dram

Non-Volatile Memory

Universal Memory

Flash Memory

10.1109/nvmsa53655.2021.9628788

Cite

Citations (2)

A One-Dimensional Depthwise Separable Convolutional Neural Network for Bearing Fault Diagnosis Implemented on FPGA

Sensors (2024)

Yu-Pei Liang Hao Chen Ching-Che Chung

This paper presents a hardware implementation of a one-dimensional convolutional neural network using depthwise separable convolution (DSC) on the VC707 FPGA development board. The design processes the one-dimensional rolling bearing current signal dataset provided by Paderborn University (PU), employing minimal preprocessing to maximize the comprehensiveness of feature extraction. To address the high parameter demands commonly associated with convolutional neural networks (CNNs), the model incorporates DSC, significantly reducing computational complexity and parameter load. Additionally, the DoReFa-Net quantization method is applied to compress network parameters and activation function outputs, thereby minimizing memory usage. The quantized DSC model requires approximately 22 KB of storage and performs 1,203,128 floating-point operations in total. The implementation achieves a power consumption of 527 mW at a clock frequency of 50 MHz, while delivering a fault diagnosis accuracy of 96.12%.

Activation function

Convolution (computer science)

10.3390/s24237831

Cite

Citations (0)