Channel length dependence of NBTI (negative bias temperature instablilty) and CHC (channel hot carrier) characteristics in PMOSFET is studied. It has been considered that HC lifetime of PMOSFET is larger than NBTI lifetime. However, it is shown that CHC degradation is greater than NBTI degradation for PMOSFET with short channel length. 1/f noise and charge pumping measurement are used for analysis of these degradations.
In this paper, we fabricated a gate-all-around bandgap- engineered (BE) silicon-oxide-nitride-oxide-silicon (SONOS) and silicon-oxide-high-k-oxide-silicon (SOHOS) flash memory device with a vertical silicon pillar type structure for a potential solution to scaling down. Silicon nitride (Si3N4) and hafnium oxide (HfO2) were used as trapping layers in the SONOS and SOHOS devices, respectively. The BE-SOHOS device has better electrical characteristics such as a lower threshold voltage (VTH) of 0.16V, a higher gm.max of 0.593µA/V and on/off current ratio of 5.76×108, than the BE-SONOS device. The memory characteristics of the BE-SONOS device, such as program/erase speed (P/E speed), endurance, and data retention, were compared with those of the BE-SOHOS device. The measured data show that the BE-SONOS device has good memory characteristics, such as program speed and data retention. Compared with the BE-SONOS device, the erase speed is enhanced about five times in BE-SOHOS, while the program speed and data retention characteristic are slightly worse, which can be explained via the many interface traps between the trapping layer and the tunneling oxide.
In this paper, the performance and the gate bias stability of amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) with different channel sputtering conditions, RF and DC are studied. DC devices show excellent electrical characteristics but larger charge trapping and slower detrapping in relaxation period under the same gate bias stress. To understand the cause of stress behavior, traps are extracted by subthreshold slop and low-high frequency dependent capacitance measurement and compared before and after gate bias stress. The extracted trap densities well explain the process-dependent device properties like as threshold voltage, mobility and on/off current ratio, but are not dependent on bias stress. From current–voltage (I–V) and capacitance–voltage (C–V) measurement, we can conclude that the threshold voltage instability arises due to the process of temporary charge trapping which is dominant only at gate bias stress and the trapping/detrapping behavior is strongly dependent on the channel layer deposition condition.
In this article, we investigated the fabrication and characteristics of Pd germanide Schottky contacts on n-type Ge substrate. It is shown that the lowest sheet resistance and uniform Pd germanide can be obtained by a one step RTP at 400°C for 30 sec. The proposed Pd germanide/nGe contact exhibited electron Schottky barrier height and work function of 0.565~0.577 eV and 4.695~4.702 eV, respectively. Therefore, the proposed Pd germanide is promising for the nanoscale Schottky barrier Ge channel MOSFETs.
A new charge pumping method is developed and applied to extract the energy distribution of nitride traps in silicon–oxide–nitride–oxide–silicon (SONOS) flash memory. Based on the Frenkel–Poole emission model and the tunneling probability given by Wentzel–Kramers–Brillouin (WKB) approximation, we proposed an advanced model of charge pumping current for SONOS device having thick tunnel oxide (>3 nm). The detection range of trap energy depth in our experiment conditions is 1.06–1.24 eV. The extracted trap density distribution in energy levels of the nitride layer of prepared sample shows the peak trap density of 1.21 ×1020 eV-1 cm-3 at 1.17 eV while the peak trap density extracted using retention model is 6.24 ×1019 eV-1 cm-3 at 1.32 eV. This difference of the peak trap density and energy level at the peak trap density is originated from different tunneling probability of tunnel oxide during the measurement.
The gate delay of ring oscillators in high V/sub T/ CMOSFET technology is characterized with respect to various channel widths (0.72 /spl mu/m-10 /spl mu/m). An expression for gate delay including the channel-width independent capacitance components is derived and compared with experimental results. Substantial increase of gate delay in the narrow channel width region is found due to channel width independent capacitance components which are inherent to transistors. Although the channel width independent capacitance is negligible in wide channel width, gate delay of narrow channel width (/spl les/1 /spl mu/m) ring oscillator increased more than 20% compared with 5 /spl mu/m channel width ring oscillator.
Microstructural changes in Si/Ti/Al/Cu (10/40/60/50 nm) Ohmic contacts to AlGaN/GaN heterostructure were investigated for complementary metal-oxide semiconductor compatible processes. Si/Ti/Al/Cu metallization exhibited a low specific contact resistance of 3.6 × 10−6 Ω-cm2 and contact resistance of 0.46 Ω-mm when a Si interfacial layer was used. Without a designated barrier metal, TiSix alloys that formed in the metallic region effectively suppressed Cu diffusion. The shallow TiN junction in AlGaN/GaN was attributed to TiSix in the metallic regions. Microstructural changes were detected by systematic physical characterization.
In order to suppress the intra-nitride charge spreading in 3D Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) flash memory where the charge trapping layer silicon nitride is shared along the cell string, N2 plasma treated on the silicon nitride is proposed. Experimental results show that the charge loss decreased in the plasma treated device after baking at 300 °C for 2 h. To extract trap density according to the location in the trapping layer, capacitance-voltage analysis was used and N2 plasma treatment was shown to be effective to restrain the interface trap formation between blocking oxide and silicon nitride. Moreover, from X-ray Photoelectron Spectroscopy, the reduction of Si-O-N bonding was observed.
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