Chiou‐Yng Lee

Lunghwa University of Science and Technology

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Co-Authors

Che Wun Chiou

Chien Hsin University of Science and Technology

Pramod Kumar Meher

Vivekananda Global University

Jim-Min Lin

Feng Chia University

Jiafeng Xie

Villanova University

Jeng‐Shyang Pan

Chaoyang University of Technology

Erl‐Huei Lu

Chang Gung University

Wen‐Yo Lee

Lunghwa University of Science and Technology

Jim‐Min Lin

Feng Chia University

Che-Wun Chiou

Chien Hsin University of Science and Technology

J.-M. Lin

Central South University

Cooperative Institutions

National Yang Ming Chiao Tung University

Chien Hsin University of Science and Technology

Chang Gung University

Lunghwa University of Science and Technology

National Cheng Kung University

Tamkang University

National Taipei University of Technology

National Tsing Hua University

Feng Chia University

National Taiwan University of Science and Technology

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Digit-Serial Systolic Karatsuba Multiplier for Special Classes over GF(2^m)

電腦學刊 (2015)

Che Wun Chiou Chiou‐Yng Lee Jim-Min Lin Yun‐Chi Yeh Hung Wei Chang

Finite field multiplication over GF (2^m) is one of the most important arithmetic operations for Elliptic Curve Cryptosystem (ECC). Polynomial basis multipliers over GF (2^m) are widely applied in ECC due to its regular, modular, easily expansible benefits and the high suitability for VLSI implementation. This study will present a novel digit-serial polynomial basis multiplier using Karatsuba algorithm representation. To achieve efficient architectures, our proposed digit-serial architecture is different from existing digit-serial polynomial basis multipliers that use cut-set algorithm. The proposed digit-serial polynomial basis multiplier saves 90% space complexity as compared to existing similar studies. Existing digit-serial polynomial basis multipliers employ one dimensional array of digit cells, but our proposed digit-serial polynomial basis multiplier uses only one digit cell.

Polynomial basis

GF(2)

Numerical digit

Modular arithmetic

Source

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Citations (4)

Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over

$\textit{GF}(2^{m})$

IEEE Transactions on Circuits and Systems I Regular Papers (2018)

Qiliang Shao Zhenji Hu Shaik Nazeem Basha Zhiping Zhang Zhiqiang Wu

Systolic finite field multiplier over GF(2 ^m ) based on the National Institute of Standards and Technology (NIST) recommended pentanomials or trinomials can be used as a critical component in many cryptosystems. In this paper, for the first time, we propose a novel low-complexity unified (hybrid field size) systolic multiplier for NIST pentanomials and trinomials over GF(2 ^m ). We have proposed a computation-corebased design strategy to obtain the desired low-complexity unified multiplier for both NIST pentanomials and trinomials. The proposed multiplier can swift between pentanomial-based and trinomial-based multipliers through a control signal. First of all, a novel strategy is briefly introduced to implement a certain matrix-vector multiplication, which can be packed as a standard computation core (or computation core like). Then, based on the computation-core concept, a novel unified multiplication algorithm is derived that it can realize both the pentanomialbased and trinomial-based multiplications. After that, an efficient systolic structure is presented that it can fully employ the introduced computation core. A detailed example of the proposed unified multiplier (for GF(2 ¹⁶³ ) and GF(2 ²³³ )) is also presented. Both the theoretical and field-programmable gate array implementation results show that the proposed design has efficient performance in area-time-power complexities, e.g., the proposed design (the one performs GF(2 ¹⁶³ ) and GF(2 ²³³ ) multiplications) is found to have at least 14.2% and 13.3% less area-delay product and power-delay product than the combination of the existing individual GF(2 ¹⁶³ ) and GF(2 ²³³ ) multipliers (best among all competing designs), respectively. Because of its structural regularity and functional flexibility, the proposed unified multiplier can be used as an intellectual property core for various cryptosystems.

Trinomial

NIST

GF(2)

10.1109/tcsi.2018.2795380

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Citations (1)

Efficient subquadratic parallel multiplier based on modified SPB of GF(2<sup>m</sup>)

2022 IEEE International Symposium on Circuits and Systems (ISCAS) (2015)

Jeng‐Shyang Pan Pramod Kumar Meher Chiou‐Yng Lee Bai Honghai

Toeplitz matrix-vector product (TMVP) approach is a special case of Karatsuba algorithm to design subquadratic multiplier in GF(2 ^m ). In binary extension fields, shifted polynomial basis (SPB) is a variable basis representation, and is widely studied. SPB multiplication using coordinate transformation technique can transform TMVP formulas, however, this approach is only applied for the field constructed by all trinomials or special class of pentanomials. For this reason, we present a new modified SPB multiplication for an arbitrary irreducible pentanomial, and the proposed multiplication scheme has formed a TMVP formula.

Trinomial

Polynomial basis

Multiplication algorithm

10.1109/iscas.2015.7168912

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Citations (3)

Concurrent Error Detection in Montgomery Multiplication over GF(2m)

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences (2006)

Che-Wun Chiou Chiou‐Yng Lee An‐Wen Deng Jim‐Min Lin

Because fault-based attacks on cryptosystems have been proven effective, fault diagnosis and tolerance in cryptography have started a new surge of research and development activity in the field of applied cryptography. Without magnitude comparisons, the Montgomery multiplication algorithm is very attractive and popular for Elliptic Curve Cryptosystems. This paper will design a Montgomery multiplier array with a bit-parallel architecture in GF(2m) with concurrent error detection capability to protect it against fault-based attacks. The robust Montgomery multiplier array with concurrent error detection requires only about 0.2% extra space overhead (if m = 512 is as an example) and requires four extra clock cycles compared to the original Montgomery multiplier array without concurrent error detection.

GF(2)

10.1093/ietfec/e89-a.2.566

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Citations (71)

Combined circuit architecture for computing normal basis and montgomery multiplications over GF(2^m)

Chin-Chin Chen Chiou‐Yng Lee Erl‐Huei Lu

Normal basis and Montgomery multiplications are two popular arithmetic operations in GF(2m). In general, each element representation has its associated different algorithm and hardware multiplication architectures. In this paper, we will present a new combined circuit for computing normal basis and Montgomery multiplications, which is based on a Hankel multiplication. The results reveal that our proposed multiplier has lower space complexity as compared to existing systolic normal basis and Montgomery multipliers. Moreover, the proposed architecture has the features of regularity, modularity and local interconnect ability. Accordingly, it is well suited for VLSI implementation.

GF(2)

Basis (linear algebra)

Polynomial basis

10.1145/1506270.1506329

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Citations (1)

Low-Complexity Bit-Parallel Systolic Multipliers over GF(2m)

Chiou‐Yng Lee Chin-Chin Chen Yuan‐Ho Chen Erl‐Huei Lu

Recently, cryptographic applications based on finite fields have attracted much interest. This paper presents two new algorithms, called time-dependent and time-independent multiplication algorithms over a finite field GF(2m) by employing an interleaved conventional multiplication and a folded technique. The proposed algorithms permit efficient realization of the bit-parallel multiplication using iterative arrays. The results show that our proposed time-dependent and time-independent multipliers save about 38% and 54% space complexity as compared to the traditional multipliers, respectively.

Realization (probability)

Multiplication algorithm

10.1109/icsmc.2006.384557

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Citations (6)

Cognitive assessment evaluation based on Blue-Red trees Inference of Rule-Space Model and social network learning

Yung‐Hui Chen Lawrence Y. Deng Chiou‐Yng Lee Huan‐Chao Keh Yi-Jen Liu

It is getting important that learning reciprocally from social network to intelligent e-learning system. In this paper, we used the Rule-Space Model to infer reasonable Blue-Red trees of learning performance and their definitions through analyzing learning objects of courses within system. We can derive social network learning grouping algorithms from previous definitions. They include one-to-one group collaborative learning algorithms. Further, we use these algorithms to build a social network learning system and apply to the Online Learning and Test System based on Analysis of Learning Performance and Social Network Learning Feedback. Besides learners are able to self-learning through Recommended Table to the Remedial Learning Objects for the Course, they can find out reasonable mutual learning targets by the suggestion of Blue-Red Trees Database of Learning Performance from the Social Network Learning System. There are the same results to improve the self-learning direction of learners and remedy the weaker learning objects for the course by internal cyclic feedback, and can also improve learning materials and items of the ITE Licenses Course by external cyclic feedback.

Instance-based learning

Proactive learning

Social Learning

Ensemble Learning

10.1109/umedia.2010.5544451

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Citations (1)

Efficient <formula formulatype="inline"><tex Notation="TeX">$M$</tex> </formula>-ary Exponentiation over <formula formulatype="inline"><tex Notation="TeX">$GF(2^{m})$</tex> </formula> Using Subquadratic KA-Based Three-Operand Montgomery Multiplier

IEEE Transactions on Circuits and Systems I Regular Papers (2014)

Chiou‐Yng Lee Pramod Kumar Meher Chien-Ping Chang

Karatsuba algorithm (KA) is popularly used for high-precision multiplication of long binary polynomials. The only well-known subquadratic multipliers using KA scheme are, however, based on conventional two-operand polynomial multiplication. In this paper, we propose a novel approach based on 2-way and 3-way KA decompositions for computing three-operand polynomial multiplications. Using these novel KA decompositions, we present here a new subquadratic Montgomery multiplier. Our proposed multiplier involves less area and less delay compared to the schoolbook three-operand multiplier as well as the two-operand multipliers based on conventional KA decomposition. We have used the proposed three-operand Montgomery multiplication to derive a novel efficient scheme for m-ary exponentiation, and proposed a novel architecture for exponentiation. We have analyzed the complexities of proposed design, and shown that the proposed exponentiator can have a small lower bound on time complexity amounting to √m-1 multiplication delays, while traditional exponentiators require nearly m multiplication delays. From synthesis results, it is shown that the proposed exponentiator using subquadratic three-operand multiplier approach has significantly less time complexity, less area-delay product, and less power consumption than the existing exponentiators. Moreover, exponentiation-based cryptosystems, such as pairing based cryptography, could achieve high-speed operation using by our proposed multiplier and m-ary exponentiator.

Operand

Exponentiation

Modular exponentiation

Multiplication algorithm

Polynomial basis

10.1109/tcsi.2014.2334992

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Citations (9)

LSM

Proceedings of the Great Lakes Symposium on VLSI 2022 (2019)

Jiafeng Xie Chiou‐Yng Lee

Unified (hybrid field-size) systolic multiplier over GF(2m) (binary extension field) has attracted significant attentions from research communities recently as it can be used in reconfigurable cryptographic processors. In this paper, we present a novel Low-complexity unified Systolic Multiplier (LSM) design strategy to address the above mentioned challenge. First, a novel multiplication algorithm for unified implementation is proposed first with detailed mathematical derivation. Then, an efficient systolic structure is then presented based on the proposed algorithm (with the help of several mapping techniques). Finally, a thorough complexity analysis is given to verify the superior performance of the proposed design (the proposed structure involves better complexities than the newly reported design).

Multiplication algorithm

10.1145/3299874.3318033

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Citations (1)

The design of a low-complexity systolic architecture for fast bit-parallel exponentiation in a class of GF(2/sup m/)

Chiou‐Yng Lee Erl‐Huei Lu Lir‐Fang Sun

Recently, bit-parallel architecture for hardware implementation in GF(2/sup m/) is of practical concern. We present a new inner product multiplication algorithm that is an alternative develop in a polynomial basis for the field GF(2/sup m/) generated by an irreducible all one polynomial (AOP). The algorithm is more efficient to construct a low-complexity bit-parallel architecture for computing AB multiplication. The complexity of the designed multiplier only requires the latency of m+2 clock delays and the complexity of basic cell comprises one 2-input AND gate, one 2-input XOR gate, and four latches. Meanwhile, the designed multiplication tree, based on the characteristic of a binary tree, uses the ideal AB multiplier to compute exponentiation in GF(2/sup m/). The latency of exponentiation only requires (m+2)[log/sub 2/m]+1 clock cycles. The cyclic time (a clock period) of our presented architectures desires one-gate delay. For the computing exponentiation in GF(2/sup m/), it turns out that our designed exponentiation is more efficient as it leads to simpler architecture and accelerates computation.

Exponentiation

Modular exponentiation

XOR gate

Polynomial basis

Multiplication algorithm

10.1109/icosp.2000.894561

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Citations (1)