Dongfan Xu

Shanghai Institute for Science of Science

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Xiongshi Luo

Southern University of Science and Technology

Hongzhi Wu

Southern University of Science and Technology

Liping Zhong

Southern University of Science and Technology

Weitao Wu

Southern University of Science and Technology

Quan Pan

Southern University of Science and Technology

Xuxu Cheng

Southern University of Science and Technology

Yangyi Zhang

First Affiliated Hospital of Zhengzhou University

Zhenghao Li

Qingdao University of Technology

Taiyang Fan

Southern University of Science and Technology

Quan Pan

Southern University of Science and Technology

Cooperative Institutions

Southern University of Science and Technology

Tokyo Institute of Technology

Institute of Science Tokyo

Shanghai Institute for Science of Science

Peng Cheng Laboratory

Tsinghua University

Hong Kong University of Science and Technology

University of Hong Kong

Chinese Academy of Sciences

Shanghai Jiao Tong University

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A 2×56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS

IEEE Journal of Solid-State Circuits (2024)

Liping Zhong Hongzhi Wu Weitao Wu Catherine Wang Wenbo Xiao

A 2

$\times$

56 Gb/s 0.78-pJ/b four pulse-amplitude modulation (PAM-4) single-ended multiple-input multiple-output (MIMO) crosstalk cancellation and signal reutilization (XTCR) receiver (RX) is investigated for medium-reach (MR) backplane communications. An XTCR scheme based on active crosstalk extraction (A-XTCR) is proposed to improve the signal reutilization efficiency of the RX. By adopting the proposed asymmetric-inductor current-mode logic (CML) single-ended-to-differential (S2D) converter, the pseudo-differential output mismatch is alleviated. Fabricated in 28-nm CMOS, the RX achieves a bit error rate (BER) of

$<$

$-$

10 at 56-Gb/s PAM-4 transmission with a channel of 24-dB Nyquist loss. Compared with the XTCR based on the conventional passive crosstalk extraction (P-XTCR), the proposed A-XTCR technique has improved vertical and horizontal eye openings of the RX by 24% and 15% at 56-Gb/s PAM-4, respectively. The result corresponds to the best energy efficiency of 0.78 pJ/b/lane, which compares favorably with the state of the art.

Crosstalk

10.1109/jssc.2024.3387355

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A 2.5dB Noise Figure 28GHz Current-Reused Noise-Cancelling LNA with g<sub>m</sub>-Boosting in 65nm CMOS for Millimeter-Wave MIMO Applications

IEICE Electronics Express (2025)

Yi Zhang Minzhe Tang Dongfan Xu J.C. Pang Hiroyuki Sakai

Extremely high frequency

Boosting

10.1587/elex.22.20250033

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A Fully-Integrated LDO with Two-Stage Cross-Coupled Error Amplifier for High-Speed Communications in 28-nm CMOS

2022 IEEE International Symposium on Circuits and Systems (ISCAS) (2023)

Dongfan Xu Yangyi Zhang Zhenghao Li Xiongshi Luo Pingyi Cai

This paper presents a fully-integrated flipped-voltage-follower-based low-dropout regulator (LDO), with proposed high-gain two-stage cross-coupled error amplifier (XCEA). Besides, the effectiveness of bypass capacitors and diversified load capacitors is discussed. Consuming $\mathbf{170}-\boldsymbol{\mu} \mathbf{A}$ quiescent current and occupying area of 0.019 mm ² , the LDO features 25-MHz unity-gain bandwidth (UGB) at 20-mA load to satisfy fast response requirement in high-speed transmitter. The simulated voltage undershoot is 38.85 mV for a load transient current stepping from $\mathbf{1}\ \boldsymbol{\mu} \mathbf{A}$ to 25 mA in 50 ps with $\boldsymbol{C}_{\mathbf{L}} =\mathbf{100}\ \mathbf{pF}$ . Owing to the proposed XCEA and the filter capacitor, the PSR is measured to be -41 dB at 100 kHz and -36 dB at 1 MHz.

10.1109/iscas46773.2023.10181630

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A 64 Gb/s/pin Single-Ended PAM-4 Transmitter With a Merged Preemphasis Capacitive-Peaking Crosstalk Cancellation Scheme for Memory Interfaces in 28-nm CMOS

IEEE Journal of Solid-State Circuits (2024)

Weitao Wu Hongzhi Wu Liping Zhong Xuxu Cheng Xiongshi Luo

Crosstalk

10.1109/jssc.2024.3509417

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7.6 A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS

2022 IEEE International Solid- State Circuits Conference (ISSCC) (2024)

Liping Zhong Hongzhi Wu Yangyi Zhang Xuxu Cheng Weitao Wu

The growing demand for cloud computing and artificial intelligence applications pushes wireline transceivers to higher data rates. DSP-based transmitters (TX) and receivers (RX) have achieved 224Gb/s [1–2], but unfortunately consume substantial power. Furthermore, 224Gb/s SerDes places more stringent demands on the signal integrity of the passive components, such as connectors, channels, and packages. In contrast, the single-ended scheme may be a practical and cost-effective solution for 224Gb/s data rates. First, it doubles the throughput density by delivering two single-ended signals over one differential channel. Furthermore, this scheme relaxes the Nyquist bandwidth for the passive components. Unfortunately, single-ended links exhibit severe crosstalk, particularly for long-channel scenarios. Previous crosstalk-cancellation (XTC) work [3] cancels the far-end crosstalk (FEXT), but at low data rates. The recent single-ended links achieve 40Gb/s/pin [4], FEXT is minimal but transmission is limited to short distances $(\lt100$ mm). This paper presents a $2 \times 112$ Gb/s PAM-4 single-ended reconfigurable XTC transceiver (TRX) employing a mismatch-mitigation single-ended-to-differential (S2D) converter and a 4-tap RX FFE in 28nm CMOS, compensating for up to 31dB loss at a power efficiency of 2.77pJ/b.

Transceiver

Crosstalk

10.1109/isscc49657.2024.10454508

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A 2 $\times$ 24 Gb/s Single-Ended Transceiver With Channel-Independent Encoder-Based Crosstalk Cancellation in 28-nm CMOS

IEEE Journal of Solid-State Circuits (2024)

Hongzhi Wu Liping Zhong Weitao Wu Catherine Wang Xuxu Cheng

Transceiver

Crosstalk

10.1109/jssc.2024.3507855

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Fully-Differential 100-Gb/s PAM4 Cross-Coupled Regulated Transimpedance Amplifier

2021 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) (2020)

Dongfan Xu Zhang Qiu Xiongshi Luo Xuewei You Wenbo Xiao

This paper describes a broadband differential regulated cascode (RGC) transimpedance amplifier (TIA) designed in 130-nm SiGe process. Cross-coupled structure and two common emitter (CE) stages feedback loop are employed to reduce input impedance. The simulation results show that the proposed TIA has 46.35-dB Ω differential transimpedance gain and 35.6-GHz bandwidth (BW). Overall, it achieves a clear 100-Gb/s PAM4 eye diagram. The total power consumption is 84mW.

Transimpedance amplifier

Cascode

Bandwidth extension

10.1109/icta50426.2020.9332048

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A 160-Gb/s 0.37-pJ/bit PAM4 Optical Receiver in 28-nm CMOS

Leiming Wang Xiongshi Luo Dongfan Xu Zhang Qiu Yiyang Yan

This paper presents a 160-Gb/s PAM4 optical receiver implemented in 28-nm CMOS process. The receiver consists of an equalized inverter-based transimpedance amplifier (TIA), a proposed 2-stage cascode-based single-to-differential converter (S2D), and a 2-stage variable gain amplifier (VGA). Inductive peaking techniques are adopted in equalized TIA and S2D for broadening bandwidth. Consuming 58.79-mW power, the proposed receiver achieves a differential conversion gain of 76.1 dBΩ with 0.2-dB and 3.2° imbalances in amplitude and phase, respectively.

Transimpedance amplifier

Variable-gain amplifier

Cascode

Video Graphics Array

10.1109/apccas55924.2022.10090288

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A 2 $\times$ 112 Gb/s/pin Single-Ended Crosstalk Cancellation Transceiver With 31-dB Loss Compensation in 28-nm CMOS

IEEE Journal of Solid-State Circuits (2024)

Liping Zhong Hongzhi Wu Yangyi Zhang Xuxu Cheng Weitao Wu

Transceiver

Crosstalk

10.1109/jssc.2024.3499376

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A 4-V_ppd160-Gb/s PAM-4 Optical Modulator Driver with All-Pass Filter-Based Dynamic Bias and 2- Tap FFE in 130-nm BiCMOS

Shuo Feng Fuzhan Chen Zhenghao Li Wentao Zhou Dongfan Xu

This paper presents a high-speed, large-output swing driver with 2-tap feed-forward equalizer (FFE) for optical modulators in 130-nm SiGe BiCMOS process. A breakdown voltage (BV) doubler topology with all-pass filter (APF)-based dynamic bias is applied in the driver to improve the output swing and the bandwidth. A 2-tap fractional-spaced FFE is implemented to compensate for the insufficient bandwidth of optical modulators. Simulation results indicate that the driver achieves an output swing of 4 $\mathrm{v}_{\text{ppd}}$ and a 3-dB bandwidth of 62.4 GHz with a power consumption of 1.15 W. The performance of the driver is further evaluated in an electrical/optical (E/O) system where a Verilog-A model for Mach-Zehnder Modulator (MZM) with a 3-dB bandwidth of 35 GHz is used. Taking advantages of the 2-tap FFE, the E/O system achieves a 3-dB bandwidth of 50.4 GHz and can support 160-Gb/s PAM-4 optical communications.

BiCMOS

10.1109/apccas55924.2022.10090363

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