A. Bryant

IBM (United States)

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Wilfried Haensch

Argonne National Laboratory

W. Noble

Gannon University

Phil Oldiges

Sandia National Laboratories

Mukesh Khare

Indian Institute of Technology Delhi

T. Standaert

IBM (United States)

T. Furukawa

Photonics Electronics Technology Research Association

E. Leobandung

IBM (United States)

Xinlin Wang

ShanghaiTech University

E. Nowak

CEA LETI

T. Kanarsky

IBM (United States)

Cooperative Institutions

IBM (United States)

215

IBM Research - Thomas J. Watson Research Center

GlobalFoundries (United States)

Albany Molecular Research (United States)

Semiconductor Research Corporation

Essex Westford School District

IBM Research - Austin

Software Research and Development Consulting

Advanced Micro Devices (Canada)

University of California, Berkeley

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Dual stress liner enhancement in hybrid orientation technology

C. Sheraw Min Yang David Fried G. Costrini T. Kanarsky

Hybrid orientation technology (HOT) has been successfully integrated with a dual stress liner (DSL) process to demonstrate outstanding PFET device characteristics in epitaxially grown [110] bulk silicon. Stress induced by the nitride MOL liners results in mobility enhancement that depends on the designed orientation of the gate, in agreement with theory. Compressive stressed liner films are utilized to increase HOT PFET saturation current to 635 uA/um I/sub DSat/ at 100 nA/um I/sub OFF/ for V/sub DD/=1.0 V at a 45 nm gate length. The AC performance of a HOT ring oscillator shows 14% benefit from [110] silicon and an additional 8% benefit due to the compressive MOL film.

Ring oscillator

Saturation current

10.1109/.2005.1469192

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Citations (24)

Parasitic leakage in DRAM trench storage capacitor vertical gated diodes

International Electron Devices Meeting (1987)

W. Noble A. Bryant Steven H. Voldman

Extensive characterization and mechanism modeling have been done on a newly observed parasitic voltage dependent junction leakage current which is inherent in the gated diodes of DRAM trench storage nodes. Excellentagreement is shown between model and data. Comparison of the observed voltage and temperature dependence to the model indicates that, in the normal range of operation, this current is limited by the diffusion of thermally generated carriers along the gated node surface. The design and reliability implications are discussed.

Dram

Shallow trench isolation

Leakage (economics)

PIN diode

10.1109/iedm.1987.191426

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Citations (15)

High-Speed Imaging with the Scanning Tunneling Microscope

A. Bryant

Source

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Citations (1)

The effects of gate field on the leakage characteristics of heavily doped junctions

IEEE Transactions on Electron Devices (1989)

W. Noble Steven H. Voldman A. Bryant

A gated-diode leakage-current mechanism is reported that is dominant below 4 V in ULSI (ultra-large-scale integration) gated-diode structures. The leakage mechanism has been fully characterized for gated junctions inherent in DRAM (dynamic random access memory) storage capacitor structures and the source-drain junctions of both PMOS (p-metal-oxide-semiconductor) and NMOS device structures. The salient features of the observed leakage current are that it is thermally activated and its magnitude increases exponentially with applied gate voltage. By making measurements at cryogenic temperatures it was possible to distinguish between the reported mechanism and that of band-to-band tunneling that occurs at higher applied voltages. A theoretical model is proposed that attributes the leakage mechanism to transport-limited thermal generation within the depleted space-charge region of the heavily doped side of junctions. An analytical expression derived from the proposed model is shown to be in excellent agreement with experimental results.< >

Leakage (economics)

Depletion region

10.1109/16.22477

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Citations (37)

Sub-25nm FinFET with advanced fin formation and short channel effect engineering

Symposium on VLSI Technology (2011)

Takashi Yamashita V. Basker T. Standaert Chun-Chen Yeh T. Yamamoto

FinFET devices achieving N/P Ion values of 1250/950 uA/um at 100nA/um at 1V, 1300/1000 uA/um with self-heating correction, are demonstrated, using a dual work function gate-first process flow at 100 nm gate pitch and 40 nm fin pitch. Ring-oscillator (RO, FO=3) functionality has been demonstrated, showing excellent Vdd scalability. We have also demonstrated logic scan chain functionality and yield improvement by optimizing the gate stack process. An optimized SIT process has been developed to improve short-channel characteristics in devices with a small number of fins in a narrow active area, which is also critical for manufacturability improvement. Various conformal doping techniques for NFET/PFET are optimized to improve device performance.

Ring oscillator

Fin

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Citations (34)

A fundamental performance limit of optimized 3.3-V sub-quarter-micrometer fully overlapped LDD MOSFET's

IEEE Transactions on Electron Devices (1992)

A. Bryant Badih El-Kareh T. Furukawa W. Noble E. Nowak

The direct experimental quantification of the relationship between gate-to-drain capacitance (C/sub gd/) and hot-electron reliability (HER) for fully overlapped LDD (FOLD) n-channel MOSFETs (NFETs) is reported. To broaden the applicability and achieve a wide range of FOLD finger lengths, the results are based on devices built using each of three different fabrication techniques. The experimentally observed tradeoff is compared to theoretical calculations to investigate its general and fundamental nature. It is shown that a peak in performance occurs at L/sub eff/ approximately=0.20 mu m for reliable 3.3-V NFETs with T/sub ox/=10 nm. Below 0.20 mu m, performance decreases due to the addition of the large FOLD fingers required to maintain adequate HER. This peak in performance can be shifted to L/sub eff/ approximately=0.15 mu m by introducing FOLD fingers only at the drain end of NFETs. For channel lengths greater than 0.25 mu m, the performances of 3.3-V FOLD NFETs and scaled 2.5-V single-diffusion NFETs are nearly equal. However, 2.5-V single-diffusion NFETs begin to offer a significant performance advantage over 3.3-V FOLD NFETs as channel lengths are reduced below 0.25 mu m.< >

10.1109/16.129105

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Citations (15)

Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond

Chung-Hsun Lin Wilfried Haensch Phil Oldiges Hailing Wang R. Williams

The nature of FinFET devices prohibits continuous width scaling and introduces a digitization of device width. As a consequence, devices are comprised of arrays of Fins ranging from one (SRAM) to a few tens of Fins. This introduces an intrinsic variation in the device that is absent in conventional planar devices. To build a reliable circuit, model parameters have to be provided that take account of the correct scaling behavior with increasing number of Fins for the composite device. For the first time we address in this paper how a composite Fin device can be modeled correctly. The statistical drive current and leakage current distribution are accurately modeled using the proposed methodology. We show that the DIBL vs. SS relationship for the composite device is an easily accessible indicator for the intrinsic variations observed in a composite device.

Ranging

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Citations (25)

Simulation Study of Multiple FIN FinFET Design for 32nm Technology Node and Beyond

Xinlin Wang A. Bryant O. Dokumaci Phil Oldiges Wilfried Haensch

Fin

Parasitic capacitance

Parasitic element

Equivalent series resistance

10.1007/978-3-211-72861-1_30

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Citations (2)

Opportunities and Challenges of FinFET as a Device Structure Candidate for 14nm Node CMOS Technology

ECS Transactions (2011)

Tenko Yamashita Veeraraghavan Basker T. Standaert Chun-Chen Yeh Johnathan Faltermeier

FinFET is a promising device candidate for 14nm node CMOS technology. We have developed FinFET device showing superior short channel control at 25nm gate length. This FinFET device featuring gate first high-k/metal gate and merged Epi source/drain process. Key process improvements to resolve the FinFET unique challenges are presented. High drive currents have been obtained for both nFET and pFET. All these results show FinFET is the most promising candidate for 14nm node CMOS technology.

Metal gate

10.1149/1.3567563

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Citations (6)

Performance comparison and channel length scaling of strained Si FETs on SiGe-on-Insulator (SGOI)

J. Cai K. Rim A. Bryant K.A. Jenkins Can Ouyang

The scaling behavior of current drive enhancements in strained-silicon NFETs on SiGe-on-insulator (SGOI) is reported. SGOI NFET enhancement exhibits only moderate channel length dependence down to sub-50 nm regime, indicating strain-induced enhancement can be sustained in future technology nodes. This is contrary to some previous reports which suggested dramatic reduction of strain-induced NFET current enhancement with channel length scaling. A novel analysis technique was developed to account for the difference in self-heating in SGOI and SOI devices to enable intrinsic device performance comparison. Additive effects of biaxial strain from the Si/SiGe heterostructure and process-induced uniaxial stress are experimentally demonstrated for the first time.

Short-channel effect

Silicon-germanium

10.1109/iedm.2004.1419097

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Citations (19)