Igor Lemberski

Riga Technical University

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Artjoms Supoņenkovs

Riga Technical University

Petr Fišer

Czech Technical University in Prague

Marina Uhanova

Riga Technical University

Viktors Gopejenko

ISMA University

Kiseon Kim

Gwangju Institute of Science and Technology

M. Koegst

Fraunhofer Society

V. G. Deı̆buk

Chernivtsi National University

B. Juurlink

Technische Universität Berlin

Aleksandrs Berezhnojs

ISMA University

РР

Р. Р. Сулейманов

Ufa Institute of Chemistry

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Ventspils University of Applied Sciences

ISMA University

Chernivtsi National University

Delft University of Technology

Riga Technical University

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Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EAS

Fraunhofer Institute for Integrated Circuits

Technische Universität Berlin

Paderborn University

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LUT‐oriented dual‐rail quasi‐delay‐insensitive logic synthesis

Electronics Letters (2014)

Igor Lemberski

The method of quasi‐delay‐insensitive logic synthesis using look‐up tables (LUTs) is described. It is shown that the dual‐rail sum‐of‐minterm function hazard‐free implementation can be done using a single LUT. Namely, instead of the conventional approach based on a DIMS representation where each minterm is implemented on a C‐element, the whole sum‐of‐minterm function is mapped into the single C‐element. For Boolean network implementation, it is proved that a fork with branches to different nodes is not required to be isochronic. It simplifies technological synthesis and allows using existing placement and routine methods and tools supposed for synchronous logic. Compared to the conventional approach, the method reduces significantly circuit complexity (in terms of the number of LUTs).

Lookup table

10.1049/el.2014.0242

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Asynchronous Logic Implementation Based on Factorized DIMS

Journal of Circuits Systems and Computers (2016)

Igor Lemberski

One of the popular methods of asynchronous logic implementation is based on so called Delay-Insensitive-Minterm-System (DIMS), where a sum-of-minterms (SOM) function is given and each minterm is represented using a state-holding (C-) element. However, such implementation is rather expensive since minterm minimization is not allowed. In the paper, structure called factorized DIMS is proposed. It is shown that under realistic delay limitation, instead of SOM, strong indication can be ensured for the sum of mutually orthogonal product terms resolved into factorized form. It reduces significant implementation complexity.

Minification

10.1142/s0218126617500876

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XILINX4000 architecture — Driven synthesis for speed

Lecture notes in computer science (1998)

Igor Lemberski M. Ratniece

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Representation

10.1007/bfb0055284

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FSM non-minimal state encoding for low power

Igor Lemberski M. Koegst Sorin Coţofană B. Juurlink

In this paper, we focus our attention on the problem of FSM state encoding for low power. In contrast to many publications where probabilistic approach to power estimation is offered, we consider power measurement based on given user-specified input sequence. Although the power dissipation depends on several parameters (register and output switching activity, complexity of combinational part, capacitance load on the gate), switching is the most important source of power dissipation. Our goal is to develop an encoding procedure which minimizes register switching activity. We start with a highly redundant (seed) encoding and minimize its length while minimizing the register switching activity. Unlike previous works, we don't restrict encoding final length (only register switching activity is considered). Therefore, final encoding length may differ from the minimal one. We tested our encoding procedure on several benchmarks from the MCNC set. The experiments show that in many cases, power dissipation obtained using our encoding (generally, of non-minimal length) is less than one achieved when encoding of minimal length is generated.

Combinational logic

10.1109/miel.2002.1003330

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Methodology of logic synthesis for implementation using heterogeneous LUT FPGAs

Igor Lemberski

Logic synthesis method for heterogeneous LUT FPGAs implementation is proposed As all example, XILINX4000 architecture is considered. The method takes XILINX4000 architectural features (heterogeneous LUTs of 3 and 4 inputs) into account and includes two step decomposition. In the first step, two-level logic representation is transformed into a graph of at most 4 fanin nodes (after this step, each node can be mapped onto 4 input LUT). In the second step, selected 4 fanin nodes are re-decomposed into 3 fanin nodes to ensure mapping onto 3 input LUTs. Re-decomposition task is formulated as substituting node two fanins for exactly one fanin.

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10.1109/glsv.1999.757424

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Dual-rail asynchronous logic multi-level implementation

Integration (2013)

Igor Lemberski Petr Fišer

Asynchronous circuit

Benchmark (surveying)

10.1016/j.vlsi.2013.02.002

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Multilevel implementation of delay-insensitive logic

Igor Lemberski Kiseon Kim

In real design, multilevel implementation is very important since logic elements have restricted number of inputs. We proposed an approach to multilevel delay-insensitive (DI) implementation of logic functions. It bases on Shannon decomposition. The multilevel DI model is given. It is shown that such implementation contains intermediate signaling. We formulated conditions the intermediate signaling can be avoided. Using our approach we processed several examples and compared two-level implementation complexity with multilevel one.

10.1109/tencon.2004.1414563

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Multi-Level Implementation of Asynchronous Logic Using Two-Level Nodes

IFAC Proceedings Volumes (2009)

Igor Lemberski Petr Fišer

Benchmark (surveying)

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Asynchronous circuit

10.3182/20091006-3-es-4010.00033

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Citations (7)

Cost Effective Implementation of Asynchronous Two-Level Logic.

World Congress on Engineering (2007)

Igor Lemberski

We proposed the cost effective (in sense of gate number) asynchronous two-level logic. It is based on AND-OR implementation of minimized logic functions. We formulated and proved the product term minimization constraint that ensures the logic correct behaviour. We pointed out the existing tool that yields the term minimization under the constraint formulated. We processed examples and generated asynchronous two-level logic by applying our approach and known ones. The implementation complexity was compared. Using our approach, we achieved significant improvement.

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Asynchronous circuit

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Method of Logic Function Multi-Level Speed-Independent Implementation

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications (2005)

Igor Lemberski Kiseon Kim

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