Kaushal Nigam

National Institute of Technology Raipur

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Dheeraj Sharma

Index Medical College, Hospital & Research Centre

P. N. Kondekar

Indian Institute of Information Technology Design and Manufacturing Jabalpur

Dharmender Nishad

Indian Institute of Technology Ropar

Satyendra Kumar

Jaypee Institute of Information Technology

Bandi Venkata Chandan

Jawaharlal Nehru Technological University, Kakinada

Sunil Pandey

Indian Institute of Technology Jodhpur

Sajai Vir Singh

ABES Engineering College

Mukesh Kumar Bind

Jaypee Institute of Information Technology

Vinay Anand Tikkiwal

Jaypee Institute of Information Technology

Km. Sucheta Singh

Sharda University

Cooperative Institutions

Indian Institute of Information Technology Design and Manufacturing Jabalpur

Jaypee Institute of Information Technology

National Institute of Technology Raipur

International Institute of Information Technology Bangalore

Manipal Academy of Higher Education

National Institute of Technology Kurukshetra

University of California, Berkeley

KU Leuven

Berkeley College

Northwestern University

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Dual-material dual-oxide double-gate TFET for improvement in DC characteristics, analog/RF and linearity performance

Applied Physics A (2019)

Satyendra Kumar Km. Sucheta Singh Kaushal Nigam Vinay Anand Tikkiwal Bandi Venkata Chandan

Ambipolar diffusion

Linearity

Capacitive coupling

10.1007/s00339-019-2650-5

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Citations (77)

Performance comparison of single and dual metal dielectrically modulated TFETs for the application of label free biosensor

Superlattices and Microstructures (2016)

Madhulika Verma Dheeraj Sharma Sunil Pandey Kaushal Nigam P. N. Kondekar

Metal gate

Tunnel field-effect transistor

10.1016/j.spmi.2016.11.045

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Citations (48)

Performance improvement of heterojunction double gate drain overlapped TFET using Gaussian doping

Sarthak Gupta Kaushal Nigam Sunil Pandey Dheeraj Sharma P. N. Kondekar

In this paper, for the first time, a Ge/Si heterojunction pocket doped double-gate-overlapped over drain tunnel FET (HP-DGODTFET) with Gaussian doping on drain side has been investigated for low-power and high frequency applications. The proposed device offers higher I _ON /I _OFF ratio in the order of (10 ¹⁴ ), steeper sub threshold swing of (14 mV/decade) and better analog/RF performance metrics using low band gap material. Further, we have analysed DC and analog/RF performance parameters for pocket doped double gate TFET (P-DGTFET), heterojunction uniform doped double gate-overlapped over drain TFET (H-DGODTFET), and heterojunction pocket doped double gate overlapped over drain TFET (HP-DGODTFET) with Gaussian doping on drain side in term of transfer characteristics, transconductance (g _m ), gate to source capacitance (C _gs ), gate to drain capacitance (C _gd ), cut-off frequency (f _T ). All the simulations for all the possible devices have been performed with the help of ATLAS device simulator.

Transconductance

10.1109/e3s.2017.8246171

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Citations (3)

Negative Capacitance FET for Ultra Low Power Applications: A Review

2022 8th International Conference on Signal Processing and Communication (ICSC) (2022)

Satyendra Kumar Km. Sucheta Singh Kaushal Nigam

Negative Capacitance Field Effect Transistor (NCFET) is turned up as a potential semiconductor device for applications in the era of advanced VLSI/ULSI technology. NCFETs have been proven as one of the promising candidate in terms of to provide steep subthreshold-slope (below 60 mV/decade) among all of the FET devices. NCFET works on the phenomenon of increasing the internal capacitance without affecting transportation mechanism. Thus, similar switching at lower supply voltage (V}}$_{\mathbf{DD}}$ has been recorded for NCFET in comparison of conventional MOS (metal-oxide-semiconductor) transistor. As NCFET offers improved DC characteristics in terms of low leakage current and high ON-current at low supply voltage, it can lead to low power consumption and less switching voltage. The formation of NCFET can be completed by incorporating a ferroelectric (FE) material layer in the gate stack of CMOS devices. This ferroelectric material provides negative capacitance effect. The presented review article provide comparative review of NCFET with Tunnel FET and MOSFET.

Subthreshold conduction

Subthreshold slope

10.1109/icsc56524.2022.10009159

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Citations (0)

Performance investigation and impact of trap charges on novel lateral dual gate oxide-bilateral tunnelling based field effect transistor

Microelectronics Reliability (2022)

Priyanka Kwatra Sajai Vir Singh Kaushal Nigam

Tunnel field-effect transistor

Transconductance

Subthreshold Swing

10.1016/j.microrel.2022.114872

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Citations (8)

A novel methodology to suppress ambipolarity and improve the electronic characteristics of polarity-based electrically doped tunnel FET

Applied Physics A (2019)

Bandi Venkata Chandan Kaushal Nigam Dheeraj Sharma Vinay Anand Tikkiwal

Ambipolar diffusion

Polarity (international relations)

Tunnel field-effect transistor

10.1007/s00339-019-2378-2

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Citations (13)

A Theoretical Performance and Reliability Investigation of a Vertical Hetero Oxide Based JL-TFET under Ideal Conditions

Silicon (2024)

Bandi Venkata Chandan Dharmender Nishad Kaushal Nigam

10.1007/s12633-024-03010-y

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Citations (4)

Group III–V ternary compound semiconductor materials for unipolar conduction in tunnel field-effect transistors

Journal of Computational Electronics (2016)

Bhagwan Ram Raad Dheeraj Sharma Kaushal Nigam P. N. Kondekar

Compound semiconductor

Ternary compound

10.1007/s10825-016-0932-0

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Citations (10)

Impact of Interface Trap Charges on Performance of Electrically Doped Tunnel FET With Heterogeneous Gate Dielectric

IEEE Transactions on Device and Materials Reliability (2017)

Pulimamidi Venkatesh Kaushal Nigam Sunil Pandey Dheeraj Sharma P. N. Kondekar

In this paper, we investigate for the first time effect of positive (donor) and negative (acceptor) interface trap charges on the performance of proposed heterogeneous gate dielectric (HD) electrically doped tunnel field-effect transistor (EDTFET) in terms of dc, analog/RF, and linearity distortion parameters, where the HD layer is considered as a gate dielectric to improve the ON-state current and device performance. For this, a comparative analysis has been performed between conventional and proposed EDTFET with identical dimensions in the presence of interface trap charges. ATLAS device simulation of both devices is performed for different performance metrics such as transfer characteristics, parasitic capacitances, device efficiency, output conductance (gds), cut-off frequency (ft), and gain bandwidth product. However, linearity distortion parameters of the proposed device such as third-order transconductance coefficient (gm3), VIP2, VIP3, IIP3, and IMD3 are also investigated. The device simulations show that HD-EDTFET is more immune in terms of performance variation than conventional EDTFET with different interface trap charges available at the Si/SiO2 interface. Thus, it can be utilized as a suitable candidate for low power analog/RF applications.

Transconductance

Linearity

10.1109/tdmr.2017.2653620

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Citations (58)

Effect of Interface Trap Charges on Performance Variation of Heterogeneous Gate Dielectric Junctionless-TFET

IEEE Transactions on Electron Devices (2017)

Sarthak Gupta Kaushal Nigam Sunil Pandey Dheeraj Sharma P. N. Kondekar

In this paper, we investigate the effect of interface trap charges on the variation of heterogeneous gate dielectric junctionless-tunnel FET (JL-TFET) by introducing both donor and acceptor type of localized charges at the semiconductor/insulator interface. In this regard, we have analyzed dc and analog/RF performance parameters for conventional and heterogeneous gate dielectric JL-TFET (HD JL-TFET) in terms of electric field, transfer characteristics, transconductance (g _m ), output transconductance (g _ds ), parasitic capacitances, device efficiency, cutoff frequency(f _T ), gain bandwidth product, and transconductance frequency product. Apart from these, linearity distortion parameters are also analyzed in the form of higher order transconductance coefficients (g _m1 , g _m2 , g _m3 ), VIP2, VIP3, IMD3, and IIP3. For this, high-K gate dielectric material (HfO ₂ ) is used in the case of the HD JL-TFET to improve the performance of the device. All the simulations for both devices have been performed with the help of an ATLAS device simulator.

Transconductance

Linearity

10.1109/ted.2017.2754297

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Citations (66)