An equivalent time sampling circuit has been developed for impulse-radio ultra-wideband radar systems. The received signals are digitized by a shifting clock. The accuracy of the clock that affects the sampling interval of analog-to-digital converter (ADC) is measured in terms of jitter and delay time. It is found that the delay time is fluctuated in every 64 times which is related to the multiplexer operation. The jitter which is calculated from the measured phase noise decreases from 85dBc/Hz to -110dBc/Hz in the low offset-frequency. It is also found that the noise from ADC degrades the some part of sampling timing and the error source is identified.
Bonding type of mercury clusters seems to vary depending on the size, kind and number of hetero-atoms and the charge state. We produced doubly charged mercury clusters and complex cluster of mercury and alkali metal by bombardment technique. The (Hg)2++ was clearly observed at half integer mass unit in the mass spectra of Hg+. The mass spectra of (Hg)nMj+ show characteristic intensity structure. We consider these mass spectra reflect the bonding types and presume them.
This paper proposes a low-power and low phase-noise current-reuse quadrature VCO using a combination of capacitor coupling and transformer feedback technique. Compared with conventional active coupled QVCO, the proposed QVCO can achieve a low phase noise characteristics with low power consumption. The proposed QVCO was fabricated in 180 nm CMOS process technology and showed a 1 MHz offset phase noise of -127 dBc/Hz at 3.97 GHz. The power consumption was 6.26 mW with 1.0 V supply voltage and a figure of merit (FOM) of the proposed QVCO was -191 dBc/Hz.
In this paper, we propose a new architecture for Capacitance-to-Digital convertor. We clarified the configuration that utilizes the time resolution of the frequency-Locked-Loop oscillator using a switched capacitor that enables stable operation, and integrated the circuit using 0.18µm standard CMOS technology. As a result, a power supply voltage of 1.2V, a capacitance resolution of 15aF, ENOB of 15.8bit, high resolution, and wide dynamic range conversion characteristics were achieved.
The size distributions of ( CsI ) n Cs + , [Formula: see text], and [Formula: see text] (M: alkali metal, j=1, 2, 3, 4, 5) clusters were obtained using secondary-ion mass spectrometry. The sizes of stable neutral clusters ( CsI ) n and ( Hg ) n clusters were determined from the mass spectra of cluster ions ( CsI ) n Cs + and ( Hg ) n M + . The magic numbers of [Formula: see text] clusters were identical to those of van der Waals type clusters. It is believed that the shell closing cluster [Formula: see text] is at the center of complex clusters [Formula: see text]. The [Formula: see text] clusters were believed to have electronic shell structures from the magic numbers.
System-on-a-chip (SoC) has become possible since a great number of circuit elements can be integrated into a single chip by the miniaturization technologies for Si CMOS. Network-onChip (NoC) has been investigated actively, and it is expected to be a new approach for designing the communication subsystems of SoC (Lee et al., 2008). Enormous circuit blocks are loaded onto the NoC, and on-chip networks like local area networks (LANs) in the NoC communicate among these circuit blocks. Since the performance of the NoC is strongly affected by on-chip networks, the construction of efficient on-chip communications infrastructures will be increasingly significant. Some of the important characteristics for on-chip interconnects are bandwidth, latency, and power. In particular, power saving technologies are very important in realizing Green IT (information technology). Power dissipation in on-chip networks mainly occurs at interconnects due to the increase of wiring resistance and capacitance. A significant issue is that power consumption of conventional on-chip interconnects, i.e. so-called RC lines, is proportional to the signal frequency; hence, it is very difficult to reduce energy dissipation per bit. Given the recent trend of high-speed signaling, we have to solve this problem and offer some good solutions. One solution is the use of copper lines and low-k dielectric, and these techniques have been widely applied and reduce power consumption for transmitting signals. However long interconnects still consume large power as in the case of RC lines. Another solution is the introduction of on-chip transmission line interconnects (TLIs). The applications of TLIs have been widely demonstrated. Modulation (Chang et al., 2003), pulsedcurrent-mode (Jose et al., 2006), current-mode-logic (Ito et al., 2004, 2005; Ishii et al., 2006; Gomi et al., 2004), low voltage differential signaling (Ito et al., 2007) and multi-drop (Ito et al., 2008) techniques are proposed, and these techniques enable the improvement of bandwidth, latency and extensibility of on-chip networks. Figure 1 is an image of on-chip networks with TLIs. It is also reported that TLIs have a better power efficiency than the conventional on-chip lines as the line length and signal frequency increase (Ito et al., 2004; Gomi et al., 2004; Ito et al., 2005; Ishii et al., 2006; Ito et al., 2007). Further improvement of the power efficiency at low frequencies is the design challenge in the case of on-chip TLIs. Since current-mode differential amplifiers are usually used for transmitters (Txs) and receivers (Rxs) in TLIs, Tx and Rx consume static power regardless ardless of the signal frequency. This means TLIs waste power if they are applied to paths with a low activity factor or to transmit low bit-rate signals.
