Armin Krieg

Infineon Technologies (Germany)

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Josef Haid

Infineon Technologies (Austria)

Christian Steger

Graz University of Technology

Johannes Grinschgl

Graz University of Technology

Holger Bock

Infineon Technologies (Austria)

Reinhold Weiß

Federal Institute for Vocational Education and Training

Norbert Druml

Infineon Technologies (Austria)

Andreas Genser

Graz University of Technology

Manuel Menghin

Graz University of Technology

Christian Kreiner

Technische Hochschule Ingolstadt

Christopher Preschern

Institute of Automation

Cooperative Institutions

Graz University of Technology

Institute of Informatics of the Slovak Academy of Sciences

Infineon Technologies (Austria)

Institut für Technische und Angewandte Physik (Germany)

Düsseldorf University Hospital

Infineon Technologies (Germany)

Heinrich Heine University Düsseldorf

Harvard University

Saarland University

Charité - Universitätsmedizin Berlin

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Hardware-Accelerated Workload Characterization for Power Modeling and Fault Injection

Armin Krieg Johannes Grinschgl Christian Steger Reinhold Weiß Holger Bock

During recent years the increasing introduction of system functionality into integrated devices resulted into several new problems for chip designers. First, high system-on-chip complexity combined with increased clock frequencies leads to power budget and thermal issues. Second, small semiconductor process structures are more sensitive to faults resulting from logic degradation and external radiation sources. Early testing and evaluation of hardware and software implementations have been enabled in the last years using hardware-accelerated emulation techniques. Such implementations rely on functional models of the target system, generated using specialized benchmark suites. These have been designed to accurately resemble typical application scenarios of the target implementation. Unfortunately, power and fault injection emulation accuracy is depending on a good coverage of the system's logic, which is not guaranteed by typical benchmarks. Therefore, this paper proposes an exhaustive hardware accelerated methodology for the evaluation of such applications and generation of accurate emulation models. The behavior of standard benchmarks are investigated using an open available system-on-chip platform based case study.

Fault injection

Hardware emulation

Benchmark (surveying)

Implementation

10.1109/ats.2012.19

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WCAP-4 IN-PILE TEST LOOP HAZARDS ANALYSIS MANUAL

C.D. Dishman R.P. Goldstein G.H. Eng A. Bournia Ray D. Berringer

From the WCAP-4 in-pile test loop information will be obtained as to how the Yankee fuel pins will withstand the high heat flux of 450,000 Btu/hr-ft/sup 2/ , pressure of 2000 psia, and temperature of 500 to 600 ction prod- F. Possible hazards associated with the operation of WCAP-4 loop experiment in the MTR are presented and each hazard and action taken to minimize or eliminate the hazard are analyzed. (W.D.M.)

Yankee

Hydrostatic test

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Principles of insect pathology.

Armin Krieg

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Solutions for Cyber-Physical Systems Ubiquity

Norbert Druml Andreas Genser Armin Krieg Manuel Menghin Andrea Hoeller

Cyber-physical system

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QEMU-Based Fault Injection for a System-Level Analysis of Software Countermeasures Against Fault Attacks

Andrea Höller Armin Krieg Tobias Rauter Johannes Iber Christian Kreiner

Physical attacks, such as fault attacks, pose a decisive threat for the security of devices in the Internet of Things. An important class of countermeasures for fault attacks is fault tolerant software that is applicable for systems based on COTS hardware. In order to evaluate software countermeasures against fault attacks, fault injection is needed. However, established fault injection approaches require manufactured products or hardware details (e.g. netlists, RTL models), which are not available when using COTS hardware. In this paper, we present a QEMU-based fault injection platform that supports commercial COTS processors that are widely-used in the embedded domain. This framework allows a system-level analysis of software countermeasures by featuring the simulation of high-level hardware faults targeting, for example, memory cells, register cells, or the correct execution of instructions. The framework supports the generation of realistic fault attack scenarios. We illustrate the practicability of the approach by presenting two exemplary use cases.

Fault injection

Software fault tolerance

10.1109/dsd.2015.79

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Citations (31)

Characterization and handling of low-cost micro-architectural signatures in MPSoCs

Armin Krieg Johannes Grinschgl Christian Steger Reinhold Weiß Andreas Genser

In recent years the wide spread introduction of small embedded systems into every corner of everyday life lead to the strong need for highly reliable and secure computing machines. These machines now affect the safety of humans as well as the security of personal data and consequently money transactions. To ensure the integrity of these systems' operating state, several fault detection mechanisms have been developed to safely correct or stop unforeseen execution behavior. Because of the rise of battery or even field-supplied systems these mechanisms often heavily decrease available power budgets or lead to significantly increased production costs. Therefore, this paper introduces novel micro-architectural execution signature characterization and handling techniques for system-on-chip designs providing power estimation hardware. Existing power sensor infrastructure is reused to enable efficient system-state monitoring using micro-architectural hashes to cover a wide range of implemented system functionality. Reduced hashing implementations are characterized for their fault detection efficiency. This hardware-based approach provides a completely transparent solution to counteract faults resulting from emerging wearout defects or intentional attacks on the execution integrity.

Implementation

10.1109/ets.2012.6233011

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Modular Fault Injector for Multiple Fault Dependability and Security Evaluations

Johannes Grinschgl Armin Krieg Christian Steger Reinhold Weiß Holger Bock

The increasing level of integration and decreasing size of circuit elements leads to greater probabilities of operational faults. More sensible electronic devices are also more prone to external influences by energizing radiation. Additionally not only natural causes of faults are a concern of today's chip designers. Especially smart cards are exposed to complex attacks through which an adversary tries to extract knowledge from a secured system by putting it into an undefined state. These problems make it increasingly necessary to test a new design for its fault robustness. Several previous publications propose the usage of single bit injection platforms, but the limited impact of these campaigns might not be the right choice to provide a wide fault attack coverage. This paper first introduces a new in-system fault injection strategy for automatic test pattern injection. Secondly, an approach is presented that provides an abstraction of the internal fault injection structures to a more generic high level view. Through this abstraction it is possible to support the task separation of design and test-engineers and to enable the emulation of physical attacks on circuit level. The controller's generalized interface provides the ability to use the developed controller on different systems using the same bus system. The high level of abstraction is combinable with the advantage of high performance autonomous emulations on high end FPGA-platforms.

Fault injection

Robustness

Abstraction

10.1109/dsd.2011.76

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Citations (16)

Hardware accelerated smart-card software evaluation supported by information leakage and activity sensors

Journal of Information Security and Applications (2013)

Armin Krieg Johannes Grinschgl Christian Steger Reinhold Weiß Holger Bock

Fault injection

Benchmark (surveying)

Implementation

Software fault tolerance

10.1016/j.jisa.2013.09.001

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[Adaptation of microorganism as a special case of differentiation].

PubMed (1956)

Armin Krieg

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Acceleration of fault attack emulation by consideration of fault propagation

Armin Krieg Johannes Grinschgl Holger Bock Josef Haid

In recent years the number of deployed embedded systems increased significantly. These system-on-chips are widely used for high-availability as well as security applications. Therefore, the reliable operation of these devices plays a vital role and disturbed operation can lead to loss of confidence and trust. To ensure correct operation during random or intentional fault events, injection techniques for system simulation and emulation have been presented. The targeted use of these approaches is often difficult because of the device complexity and the lack of knowledge about internal processes after a fault has been activated. To improve the current state-of-the-art in this field this paper presents fault propagation analysis and hardware checker generation techniques based on static VHDL code analysis. These help to gain a deeper understanding of system internal propagation paths and their influence on normal operation. Physical layout data is included to enable the mapping of a fault attack location to its corresponding logic gates. Hardware checkers enable higher fault injection evaluation efficiency by removing masked system parts from the target space.

Fault injection

Hardware emulation

Fault model

10.1109/fpt.2012.6412141

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Citations (1)