Nowadays, two innovative future trends regarding hardware development and hardware description can be found. The first trend concerns the hardware itself. Modern Xilinx FPGAs provide the possibility to be reconfigured partially and dynamically - which is called dynamical partial reconfiguration (DPR). DPR opens a huge field of new functionalities on FPGAs. However, using DPR means struggling with architectural details of the used FPGAs and the according synthesis and implementation tools. A developer would focus most of the time on DPR and only a small part of the time on the implementation of the actual modules - of course that is the opposite of what hardware engineers want to do. The second trend concerns the way hardware is described. Many hardware developing groups are looking forward to an HDL which operates on the algorithmic level, since this would come with a significant increase in productivity. The aim is to be able to translate common software algorithms to hardware in an efficient way (which is called high-level synthesis or HLS). Although both DPR and HLS are important future trends regarding hardware design, they develop quite independently. Today's software-to-hardware compilers focus on conventional hardware and therefore have to remove dynamic aspects such as the instantiation of calculating modules at runtime. Even object-oriented languages like SystemC do not support the dynamic instantiation of objects (that means the usage of new or delete outside of the constructor) for synthesis at all. On the other hand, DPR tools are working on the lowest possible layer regarding FPGAs: the bitfile level. Our research focuses on the design and the implementation of a Framework combining the two technologies, since this has the potential to kill two birds with one stone. Firstly, DPR can change the programming paradigm in future HDLs regarding dynamic instantiations. Dynamic parts would not have to be removed any longer but could be realized on the target FPGA using DPR. Secondly, a high-level language support of DPR technologies could help end its shadowy existence and turn it into a commonly used method.

Control reconfiguration

High-Level Synthesis

Reconfigurable Computing

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ReConFig 2018 Best Paper Award

W. Kamp N. Abel G. Comoretto

10.1109/reconfig.2018.8641690

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Complex Multiply Accumulate Cells for the Square Kilometre Array Correlators

W. Kamp N. Abel G. Comoretto

This paper presents FPGA designs and design optimisations for the complex multiply accumulate cells (CMACs) that are the basic building block of the Square Kilometre Array (SKA) correlators. The CMACs use a novel signal encoding technique to pack a complex multiplication into a single integer multiplication. This halves the number of hard multiplier blocks required to implement the SKA correlators. Designs are presented for use in both the Mid and Low Correlator Beamformers (CBF), which employ Intel Stratix10 and Xilinx UltraScale + FPGAs respectively. Further optimisations enable a reduction in the correlator resources by approximately 40%. These optimisations allow Mid.CBF and Low.CBF to put all required functionality into a minimal number of FPGAs, thereby saving cost and most importantly power.

Square (algebra)

SIGNAL (programming language)

10.1109/reconfig.2018.8641708

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The CBM Collaboration

Nuclear Physics A (2009)

N. Abel Jakub Adamczewski D. Adamova Monica Aggarwal Nazar Farid Ahmad

10.1016/j.nuclphysa.2009.10.145

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Design and Implementation of an Object-Oriented Framework for Dynamic Partial Reconfiguration

N. Abel

This paper focuses on the design and the implementation of a Framework combining the two technologies. Firstly, dynamical partial reconfiguration (DPR) which can change the programming paradigm in future hardware description languages (HDL) regarding dynamic instantiations. Dynamic parts would not have to be removed any longer but could be realized on the target FPGA using DPR. Secondly, a high-level language support of DPR technologies could help end its shadowy existence and turn it into a commonly used method. The object-oriented DPR Framework enables hardware developers to write reconfigurable modules without going into detail with the reconfiguration techniques. The reconfigurable modules are described in a high-level language called POF. Since POF is very similar to Java, it makes use of well-known programming constructs. This makes the handling of the whole reconfiguration process much easier and helps increase the productivity significantly.

Control reconfiguration

Java Programming Language

Reconfigurable Computing

10.1109/fpl.2010.55

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Citations (20)

Alignment of the ALICE Inner Tracking System with cosmic-ray tracks

Journal of Instrumentation (2010)

K. Aamodt N. Abel U. Abeysekara A. Abrahantes Quintana D. Adamová

ALICE (A Large Ion Collider Experiment) is the LHC (Large Hadron Collider) experiment devoted to investigating the strongly interacting matter created in nucleus-nucleus collisions at the LHC energies. The ALICE ITS, Inner Tracking System, consists of six cylindrical layers of silicon detectors with three different technologies; in the outward direction: two layers of pixel detectors, two layers each of drift, and strip detectors. The number of parameters to be determined in the spatial alignment of the 2198 sensor modules of the ITS is about 13,000. The target alignment precision is well below 10 μm in some cases (pixels). The sources of alignment information include survey measurements, and the reconstructed tracks from cosmic rays and from proton-proton collisions. The main track-based alignment method uses the Millepede global approach. An iterative local method was developed and used as well. We present the results obtained for the ITS alignment using about 105 charged tracks from cosmic rays that have been collected during summer 2008, with the ALICE solenoidal magnet switched off.

Tracking (education)

10.1088/1748-0221/5/03/p03003

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Citations (332)

Charged-particle multiplicity measurement in proton–proton collisions at $\sqrt{s}=0.9$ and 2.36 TeV with ALICE at LHC

The European Physical Journal C (2010)

K. Aamodt N. Abel U. Abeysekara A. Abrahantes Quintana A. Abramyan

Charged-particle production was studied in proton-proton collisions collected at the LHC with the ALICE detector at centre-of-mass energies 0.9 TeV and 2.36 TeV in the pseudorapidity range |$η$| < 1.4. In the central region (|$η$| < 0.5), at 0.9 TeV, we measure charged-particle pseudorapidity density dNch/deta = 3.02 $\pm$ 0.01 (stat.) $^{+0.08}_{-0.05}$ (syst.) for inelastic interactions, and dNch/deta = 3.58 $\pm$ 0.01 (stat.) $^{+0.12}_{-0.12}$ (syst.) for non-single-diffractive interactions. At 2.36 TeV, we find dNch/deta = 3.77 $\pm$ 0.01 (stat.) $^{+0.25}_{-0.12}$ (syst.) for inelastic, and dNch/deta = 4.43 $\pm$ 0.01 (stat.) $^{+0.17}_{-0.12}$ (syst.) for non-single-diffractive collisions. The relative increase in charged-particle multiplicity from the lower to higher energy is 24.7% $\pm$ 0.5% (stat.) $^{+5.7}_{-2.8}$% (syst.) for inelastic and 23.7% $\pm$ 0.5% (stat.) $^{+4.6}_{-1.1}$% (syst.) for non-single-diffractive interactions. This increase is consistent with that reported by the CMS collaboration for non-single-diffractive events and larger than that found by a number of commonly used models. The multiplicity distribution was measured in different pseudorapidity intervals and studied in terms of KNO variables at both energies. The results are compared to proton-antiproton data and to model predictions.

Pseudorapidity

Multiplicity (mathematics)

Antiproton

10.1140/epjc/s10052-010-1339-x

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Citations (203)

03 - Traitement temps réel des images en exploitant la reconfiguration dynamique : architecture et programmation

Traitement du signal (2006)

Lounis Kessal N. Abel Didier Demigny

Le projet ARDOISE 1 vise a demontrer l'interet des architectures materielles a reconfiguration dynamique (RD) dans les systemes associant contraintes temps reel fortes et versatilite des traitements. A l'heure actuelle, ARDOISE est la seule architecture developpee en France, dont un prototype a effectivement ete realise et teste en situation reelle, qui mette en oeuvre ce concept. Cet article presente les principaux resultats obtenus: definition d'une architecture de test, definition de metriques generiques guidant le parametrage de mise en oeuvre de la RD, strategies de partitionnement des algorithmes sur le materiel, outils de compilation et de gestion temps reel des configurations, test sur une gestion dynamique de traitements d'images temps reel.

Control reconfiguration

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Précis d'une theorie des fonctions elliptiques. (Suite).

Journal für die reine und angewandte Mathematik (Crelles Journal) (1829)

N. Abel

26.Precis d'une theorie des fonctions ellipticpes.(Suite du memoire 19.cab.dem.) (Par Mr. N. H, Abel de Cliristiama.) C h a p i t rIV.De Toquation (l-y*)(l -c'V) =r r*(l-• **)(! -c*x*).VJonsidorons maintenant le probteme (^), savoir de satisfaire de Ja maiiiere la plus gonerale ä F&juation:118. (l -y*)(l -*'V) = r a (l -a^)(l-c*x*\ y et r otant des fonctions rationnelles de x.La mithode qui s'ojBTre dV bord de rosoudre ce probleme est celle des coefficiens indoterminos, mais cette methode ne paroit guere applicable, si le degr^ de la fonction y est un peu elevoj au moins sön application sei^oit tres penible.Je vais prosenter une autre, plus simple et qui est ; ce nie ^ejpble, iippprtante dans la thoorie des fonctions elliptiques, Reductiön du probleme a celul de satisfaire a On Toit d'abord gue si Te^uation dont il s^git a Heu, on dtrit avoir necessairementoü e est constant.11 est facile de voir que les deux facteurs l -y f , l -c'*'y* ne peuvent s'ovanouir en möme tems, oar dans ce cas on auröit _ ^y2 = ^.? / ou r x et r s soat des fonctions rationnelles dont le jproduit est egal a r.

10.1515/crll.1829.4.309

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Citations (22)