Fangxu Lv

National University of Defense Technology

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Xuqiang Zheng

Institute of Microelectronics

Mingche Lai

National University of Defense Technology

Zhihua Wang

Tsinghua University

Jianye Wang

Hangzhou Dianzi University

Chaolong Xu

National University of Defense Technology

Hanjun Jiang

Tsinghua University

Yajun He

Tsinghua University

Geng Zhang

National University of Defense Technology

Ziqiang Wang

Gansu Provincial Hospital

Xinyu Liu

Institute of Microelectronics

Cooperative Institutions

Chinese Academy of Sciences

National University of Defense Technology

Institute of Microelectronics

Tsinghua University

Air Force Engineering University

University of Chinese Academy of Sciences

Sichuan University

Southeast University

Huazhong University of Science and Technology

Zhejiang University

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A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS

Microelectronics Journal (2022)

Mingche Lai Geng Zhang Fangxu Lv Xuqiang Zheng Heming Wang

This paper presents a low-power, high-bandwidth wireline transceiver for chiplet. The transceiver uses a new technology of correlated non-return to zero (CNRZ) to improve the pin efficiency and reduce the noise of the common mode and crosstalk (CMN and XTALK). The transmitter adopts a 4:1 multiplexer (MUX) and a special voltage-mode driver [source series terminated (SST)] to improve the power efficiency. The receiver utilizes a low jitter clock-and-data alignment (CDA) based on high resolution phase interpolator (PI) and a MINI-PLL with differential filter based to improve the jitter performance of the receiver's clock. In addition, a special continuous-time linear equalizer (CTLE) is introduced into the multiple-input compare (MIC) based decode circuit to reduce the receiver's bit error rate (BER). This transceiver is designed with a 28 nm CMOS process technology and supplied with 0.9/1.2 V. Simulation results show that this transceiver can operate at 200 Gb/s with the 33.3 Gb/s single-wire data rate and a power consumption of 1.06 pJ/b. The transceiver's BER is less than 1E-15 and eye-wide-opening is 12.02 ps (48.08% UI), which is under 10 dB channel loss at 20 GHz Nyquist frequency.

Transceiver

SerDes

Wireline

Electrical efficiency

10.1016/j.mejo.2022.105628

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Citations (3)

A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) (2019)

Hao Ding Xuqiang Zheng Danyu Wu Lei Zhou Jin Wu

This letter presents a 112-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter with a 2-tap fractional-spaced feed-forward equalizer (FFE) implemented in a 65-nm CMOS process. The tap delay is adjusted by a coarse-fine capacitor array-based delay cell located in the clock path. Dynamic latches, pseudo-AND2s, and bandwidth-enhanced 4:1 MUXs are employed to guarantee an adequate timing margin and a sufficient bandwidth for the 112-Gb/s design. The measurement results show that the fractional-spaced FFE can significantly optimize the eye opening. The fabricated PAM-4 transmitter achieves a maximum data rate of 112 Gb/s with an energy efficiency of 2.17 pJ/bit.

10.1109/esscirc.2019.8902616

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A 10 GHz 56 fs<inf>rms</inf>-integrated-jitter and −247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS

2022 IEEE Custom Integrated Circuits Conference (CICC) (2017)

Xuqiang Zheng Fangxu Lv Feng Zhao Shigang Yue Chun Zhang

This paper presents a low jitter ring-VCO based injection-locked clock multiplier (RILCM) with a phase-shift detection based hybrid frequency tracking loop (FTL). A fullswing pseudo-differential delay cell (FS-PDDC) is proposed to lower the device noise to phase noise conversion. To obtain high operation speed, high detection accuracy, and low output disturbance, a compact timing-adjusted phase detector (TPD) tightly combining with a well-matched charge pump (CP) is designed. Additionally, a lock-loss detection and lock recovery (LLD-LR) scheme is devised to equip the RILCM with a similar lock-acquisition ability to conventional PLL, thus excluding the initial frequency setup aid and preventing potential lock loss. Implemented in 65 nm CMOS, the RILCM occupies an active area of 0.07 mm ² and consumes 59.4 mW at 10 GHz. The measured results show that it achieves 56.1 fs rms-jitter and - 57.13 dBc spur level. The calculated figure-of-merit (FOM) is -247.3 dB, which is better than previous RILCMs and even comparable to those large-area LC-ILCMs.

dBc

Ring oscillator

Phase frequency detector

Figure of Merit

10.1109/cicc.2017.7993597

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Citations (5)

A High Speed and Low BER Dual-mode Adaptive Equalizer Using Hybrid Parallel DFE

IEICE Electronics Express (2024)

Xiaoyue Hu Fangxu Lv Mingche Lai Zhang Luo Qiang Wang

Dual mode

Adaptive equalizer

Mode (computer interface)

10.1587/elex.21.20240417

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A High Speed Adaptive Reflection Cancellation Equalization Circuit with Floating Tap Ffe and Loop-Refactored Dfe for Adc-Dsp-Based Wireline Reciver

Cewen Liu Xingyun Qi Fangxu Lv Qiang Wang Liquan Xiao

High speed communication networks depend on higher data rates for bandwidth expansion, but face challenges in maintaining signal integrity when data rates exceed 100 Gb/s due to ISI and reflection, which hinder transmission speed advancements.This paper proposes the design of an adaptive reflection cancellation circuit for high-speed 4-level pulse amplitude (PAM4) serializer-deserializer (Serdes) receiver based on analog-to-digital converter (ADC) + digital signal processing (DSP) architecture.The proposed parallel Floating Tap Feedforward equalization(FT-FFE) effectively mitigates the impact of reflection without the need for a large number of equalizers, thereby reducing power consumption overhead. A Loop-Refactored decision feedback equalizer (LR-DFE) is implemented to mitigate timing constraints in ADC-DSP based high-speed wireline receivers, improving system performance and timing reliability.The tap coefficients are adaptively updated in combination with the Least Mean Square (LMS) algorithm.Simulation and FPGA platform validation results demonstrate that at a data rate of 56Gb/s, the bit error rate(BER) is below 1e-12 through a channel with 39dB insertion loss(IL).

SerDes

Wireline

Adaptive equalizer

10.2139/ssrn.5087411

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An Analytical Jitter Transfer Model for Mueller-Muller Clock and Data Recovery Circuits

2021 IEEE 14th International Conference on ASIC (ASICON) (2021)

Tao Liu Fangxu Lv Bin Liang Heming Wang Jianye Wang

This paper describes a segmentation model to predict the key characteristic of a Mueller-Muller clock and data recovery circuits (MM-CDR): namely, jitter transfer. On the one hand, the model linearizes the gain of the Mueller-Muller phase detector (MMPD) using its jitter characteristics, then obtains the jitter transfer function in the linear region; on the other hand, according to a large signal critical behavior characteristic of MM-CDR, the jitter transfer function in the nonlinear region is obtained. The experiments all show excellent conformance between analytical equations and simulation results.

SIGNAL (programming language)

10.1109/asicon52560.2021.9620396

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Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator

IEEE Transactions on Circuits & Systems II Express Briefs (2023)

Kewei Xin Mingche Lai Fangxu Lv Xuqiang Zheng Kaile Guo

This paper proposes a frequency domain model for injection-locked LC oscillators by introducing the impulse sensitivity function (ISF) and injection factor, analyzes the effect of the injection pulse width and injection position on oscillator performance based on this model, and derives an equation that can guide the design and optimization of oscillators. The model fills the gap in the field of frequency domain models for injection-locked LC oscillators. Based on the above model, a clock generator circuit structure operating at 14 GHz, combining a phase-locked loop with an injection-locked oscillator, is designed and measured based on a 65-nm cmos process. The circuit achieves better phase noise performance by optimizing the two parameters, which verifies the accuracy of the proposed model.

Injection locking

Clock generator

Colpitts oscillator

10.1109/tcsii.2023.3296778

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Citations (1)

A 4-40 Gb/s PAM-4 transmitter with a hybrid driver in 65 nm CMOS technology

Dengjie Wang Hong Chen Wenhuan Luan Xin Lin Fangxu Lv

This paper presents a 4-40 Gb/s PAM-4 transmitter using a novel hybrid driver. Different from conventional current-mode (CM) drivers with poor linearity and source-series terminated (SST) drivers with limited differential output swing, the proposed hybrid driver delivers a differential output swing exceeding the supply voltage with high linearity using a combination structure of the CM and SST driver. In addition, a 4-40 Gb/s quarter-rate transmitter with one-tap feedforward equalization is designed in 65nm CMOS technology using the hybrid driver, yielding a 1.8V differential peak-to-peak output swing at 1.2 V supply voltage with a 96.4% ratio of level mismatch.

Linearity

10.1109/mwscas.2019.8885140

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A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology

2021 IEEE 14th International Conference on ASIC (ASICON) (2015)

Fangxu Lv Xuqiang Zheng Ziqiang Wang Jianye Wang Fule Li

This paper presents a 50Gb/s low power PAM4 transmitter with 4-tap FFE and high linearity output voltage. By employing a low voltage cascode current mirror under the output driver, the nonlinearity between the high and low bit output current is reduced. In addition, the output Vpp reaches 1V. Replacing the hungry CML latch by the transmission gate and realizing the data delay for pre-emphasis at former stage, the consumption of the transmitter is reduced at this high rate. Simulation result shows that, the four-level-signal has clear eye diagram when passing through a channel model with 14.3dB attenuation at 12.5GHz. The output has minimum vertical eye opening of 119mVpp and minimum horizontal eye width of 21ps (0.52UI). The active chip area of the whole transceiver is 0.61mm × 0.92mm. Performed in 65 nm CMOS technology, the transmitter running at 50Gb/s consumes 66mW power under 1.2 V supply.

SerDes

Transceiver

Linearity

Cascode

Transmission gate

10.1109/asicon.2015.7516921

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Citations (1)

A Low Jitter and Low Reference Spur 5GHz PLL with Quadrature Charge-sampling PD in 28nm CMOS Process

IEICE Electronics Express (2024)

Wenchen Wang Fangxu Lv Zhengbin Pang Heng Huang Zhang Luo

Spur

Quadrature (astronomy)

10.1587/elex.21.20240375

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