Future 100Gbaud DSP-enabled optical coherent transceivers [1] will need 100GS/s DACs with an analog bandwidth (BW) of at least 50GHz to support advanced modulation schemes. CMOS-based DACs are preferred because they support monolithic integration of the DSP and DAC, but the achievable sampling rate and BW is limited [2]. To increase the sampling rate, multiple DACs can be passively or actively combined. A passive combiner using a distributed topology [3] increases the DAC sampling rate to 100GS/s with an analog BW of 13GHz. A 200GS/s linear active combiner with 44GHz analog BW is demonstrated in [4] using a bipolar process. Such linear combiner schemes [3], [4] extend their spurious-free dynamic range by adding the outputs of two complementary clocked DACs and cancelling the images in the even Nyquist zones, however, fundamentally their output analog BW cannot extend beyond the Nyquist frequency of the sub-DACs. Alternatively, time domain interleaving of DACs can be used. A 2-to-1 analog multiplexer (AMUX) using 130nm SiGe BiCMOS is reported in [5] with an analog BW >67GHz. Its measured sampling rate is 56GS/s. The 2-to-1 AMUX from [6] achieved>110GHz analog BW at 180GS/s using a 0.25μm InP HBT process, however it requires digital pre-processing to compensate the limited switching speed [7]. We report a 4-to-1 interleaver with an analog BW beyond Nyquist at sampling rates up to 100GS/s using SiGe BiCMOS. The interleaver is based on the generation and summation of return-to-zero (RZ) signals from analog input signals. The advantage of the architecture is that it can simultaneously perform equalization to e.g. compensate interconnect losses at its output and cancels clock feedthrough.
As next-generation data center optical interconnects aim for 0.8 Tb/s or 1.6 Tb/s, serial rates up to 106 GBd are expected. However doubling the bandwidth of current 53 GBd 4-level pulse-amplitude modulation (PAM-4) transmitters is very challenging, and perhaps unfeasible with compact, non-travelling wave, lumped modulators or lasers. In our previous work, we presented an integrated 4:1 optical serializer with electro-absorption modulators (EAMs) in each path. Transmitter (TX) functionality was shown up to 104 GBd non-return-to-zero (NRZ) On-Off Keying (OOK) or PAM-4. However the performance for PAM-4 was limited by the distortion introduced by the EAM non-linearity. We also presented a real-time, DSP-free 128 Gb/s PAM-4 link with a silicon photonic transmitter using binary driven EAMs in a Mach-Zehnder interferometer (MZI) configuration. By combining two of such half-rate (53 GBd) transmitters in an integrated 2:1-serializer, improved 106 GBd PAM-4 performance is expected without needing to compensate the inherent modulator non-linearity and without requiring faster modulators or drivers. In this paper, we present a Silicon integrated 53 GBd PAM-4 TX as a candidate for integration into 106 GBd PAM-4 2:1 serialized TX. The presented TX consists of two EAMs in an MZI configuration, wirebonded to a low-power 55 nm 4-channel SiGe BiCMOS driver, operating at 1.5 pJ/b (excluding laser). With a reference receiver (RX), transmission at or below the KP4-FEC threshold is shown beyond 1km standard single-mode fiber (SSMF) and up to 2 km non-zero dispersion-shifted fiber (NZ-DSF) at 1565 nm. Furthermore, the integrated TX was combined with an Si-integrated RX consisting of the same EAM component, wirebonded to a 55 nm SiGe BiCMOS transimpedance amplifier (TIA). Both TX and RX were wirebonded on an RF-PCB, with electrical connectivity through transmission lines and 6-inch 50 GHz multi-coax cable connectors. With this electrically connectorized all-EAM TX and RX, PAM-4 link operation is shown up to 40 GBd at 3.9 pJ/b (excluding laser), without using DSP or equalization.
We demonstrate an optical transmitter consisting of a limiting SiGe BiCMOS driver co-designed and co-packaged with a silicon photonic segmented traveling-wave Mach-Zehnder modulator (MZM). The MZM is split into two traveling-wave segments to increase the bandwidth and to allow a 2-bit DAC functionality. Two limiting driver channels are used to drive these segments, allowing both NRZ and PAM4 signal generation in the optical domain. The voltage swing as well as the peaking of the driver output are tunable, hence the PAM4 signal levels can be tuned and possible bandwidth limitations of the MZM segments can be partially alleviated. Generation of 50 Gbaud and 53 Gbaud PAM4 yields a TDECQ of 2.8 and 3.8 dB with a power efficiency of 3.9 and 3.6 pJ/bit, respectively; this is the best reported efficiency for co-packaged silicon transmitters for short-reach datacenter interconnects at these data rates. With this work, we show the potential of limiting drivers and segmented traveling-wave modulators in 400G capable short-reach optical interconnects.
We demonstrate a four-to-one 100-GS/s time interleaver realized in a 55-nm BiCMOS technology. The interleaver comprises two stages of two-to-one sub-interleavers. Each sub-interleaver is implemented using a return-to-zero generation and summing architecture. This sub-interleaver architecture ensures lower clock feedthrough and contains an inherent feed-forward equalizer. Effective number of bits (ENOB) measurements have been performed revealing the interleaver's ENOB of 4.9 at 3 GHz. In addition, the transfer function is measured to show the capabilities of the inherent feed-forward equalizer of the sub-interleavers. The measured analog output bandwidth of the four-to-one interleaver is 73 GHz. Finally, a 100-GBd PAM-4 (200 Gb/s) signal is generated by interleaving four 25-GBd PAM-4 streams while consuming 700 mW.
We present progress on high-speed electronic ICs for Silicon Photonic transceivers. The design freedom offered by Silicon Photonics is exploited to generate multilevel modulation formats, reduce power consumption and physical footprint or increase speed. We show drivers and receivers integrated in CMOS and SiGe BiCMOS processes.
To address the challenges of the Digital Agenda for Europe (DAE) and also to remain in line with the evolution of terrestrial communications in a globally connected world, a major increase in telecoms satellites capacity is required in the near future. With telecom satellites payloads based on traditional RF equipment, increase in capacity and flexibility has always translated into a more or less linear increase in equipment count, mass, power consumption and power dissipation. The main challenge of next generation of High Throughput Satellites (HTS) is therefore to provide a ten-fold-increased capacity with enhanced flexibility while maintaining the overall satellite within a "launchable" volume and mass envelope [1], [2], [3]. Photonic is a very promising technology to overcome the above challenges. The ability of Photonic to handle high data rates and high frequencies, as well as enabling reduced size, mass, immunity to EMI and ease of harness routing (by using fibre-optic cables) is critical in this scenario.
New circuit architectures and technologies for high-speed electronic and photonic integrated circuits are essential to realize optical interconnects with higher symbol rate. As a consequence of the increasing speeds, close integration and co-design of photonic and electronic chips have become a necessity to realize high-performance transceivers with novel packaging approaches. Extensive co-design also enables the design of new electro-optic architectures to create and process optical signals more efficiently. This paper and presentation will illustrate a number of recent developments of application-specific high-speed electro-optic transceiver circuits including e.g. broadband driver amplifiers, transimpedance amplifiers, analog equalizers and multiplexer circuits for signal generation and reception at 100 Gbaud and beyond. The basic concepts and architectures, technological aspects, design challenges and trade-offs will be discussed.
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