New generations of ULSI devices require significant improvements in circuit overlay. The performance limits of a current wafer stepper alignment system have been evaluated by testing alignment target capture on planarized targets and rough substrates. Although new hardware is being developed for alignment under difficult conditions, it has been shown that new algorithm designs can extend the performance of existing systems.
In the development and manufacture of integrated circuits, as requirements push closer to the theoretical (Rayleigh) limit of performance, depth of focus decreases as resolution is increased. The advent of easily accessible tools for image processing suggest that a quantitative determination of best focus is possible. Workers in this laboratory have developed a technique for determining `best focus' using 2-D Fourier power spectra of SEM images of exposed patterns. From this a `figure of merit' is extracted by assuming that what is desired is to maximize orthogonal edges (from `as-drawn' features) and minimize intermediate features (edge rounding). This has been shown to provide a quantitative value that is consistent with an `expert' assessment of the same images. The system is consistent with automation of the process, eliminating the need to record hard-copy images for `expert' evaluation.
The use of scanning deep level transient spectroscopy (SDLTS) in the investigation of deep level trap distributions in LEC GaAs is described. Technique is based on electron beam induced current transients in a Schottky barrier, allowing approx. 1 micron spatial resolution. Results indicating enhanced hole trap concentrations around dislocation cores and walls are presented.
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