MÁ

Mauricio Álvarez-Mesa

Spintronics Research Network of Japan

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Ben Juurlink

Technische Universität Berlin

Chi Bun Ching

National Taiwan University Hospital

Cor Meenderinck

Delft University of Technology

Arnaldo Azevedo

Delft University of Technology

Alex Ramírez

Wayne State University

Thomas Schierl

Fraunhofer Institute for Telecommunications, Heinrich Hertz Institute

Jan Lucas

Technische Universität Berlin

Sergio Sanz-Rodríguez

Technische Universität Berlin

Philipp Habermann

Technische Universität Berlin

Sohan Lal

Hamburg University of Technology

Cooperative Institutions

Technische Universität Berlin

Universitat Politècnica de Catalunya

Barcelona Supercomputing Center

Fraunhofer Institute for Telecommunications, Heinrich Hertz Institute

Delft University of Technology

Poznan Supercomputing and Networking Center

Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento

University of Lisbon

Poznań University of Technology

Embedded Systems (United States)

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GPGPU workload characteristics and performance analysis

Sohan Lal Jan Lucas Michael Andersch Mauricio Álvarez-Mesa Ahmed Elhossini

GPUs are much more power-efficient devices compared to CPUs, but due to several performance bottlenecks, the performance per watt of GPUs is often much lower than what could be achieved theoretically. To sustain and continue high performance computing growth, new architectural and application techniques are required to create power-efficient computing systems. To find such techniques, however, it is necessary to study the power consumption at a detailed level and understand the bottlenecks which cause low performance. Therefore, in this paper, we study GPU power consumption at component level and investigate the bottlenecks that cause low performance and low energy efficiency. We divide the low performance kernels into low occupancy and full occupancy categories. For the low occupancy category, we study if increasing the occupancy helps in increasing performance and energy efficiency. For the full occupancy category, we investigate if these kernels are limited by memory bandwidth, coalescing efficiency, or SIMD utilization.

Occupancy

Electrical efficiency

Performance Improvement

SIMD

10.1109/samos.2014.6893202

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Citations (9)

PSNC advanced multimedia and visualization infrastructures, services and applications

Zenodo (CERN European Organization for Nuclear Research) (2018)

Krzysztof Kurowski Maciej Głowiak Bogdan Ludwiczak Maciej Strozyk Miłosz Ciżnicki

10.5281/zenodo.3973105

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Parallel HEVC Decoding on Multi- and Many-core Architectures

Journal of Signal Processing Systems (2012)

Chi Bun Ching Mauricio Álvarez-Mesa Jan Lucas Ben Juurlink Thomas Schierl

Multi-core processor

Frame rate

Laptop

10.1007/s11265-012-0714-2

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Citations (31)

Understanding the Application: An Overview of the H.264 Standard

SpringerBriefs in computer science (2012)

Ben Juurlink Mauricio Álvarez-Mesa Chi Bun Ching Arnaldo Azevedo Cor Meenderinck

Scalable Video Coding

Context-adaptive variable-length coding

10.1007/978-1-4614-2230-3_2

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Citations (13)

Application-Specific Cache and Prefetching for HEVC CABAC Decoding

IEEE Multimedia (2017)

Philipp Habermann Chi Bun Ching Mauricio Álvarez-Mesa Ben Juurlink

Context-based Adaptive Binary Arithmetic Coding (CABAC) is the entropy coding module in the HEVC/H.265 video coding standard. As in its predecessor, H.264/AVC, CABAC is a well-known throughput bottleneck due to its strong data dependencies. Besides other optimizations, the replacement of the context model memory by a smaller cache has been proposed for hardware decoders, resulting in an improved clock frequency. However, the effect of potential cache misses has not been properly evaluated. This work fills the gap by performing an extensive evaluation of different cache configurations. Furthermore, it demonstrates that application-specific context model prefetching can effectively reduce the miss rate and increase the overall performance. The best results are achieved with two cache lines consisting of four or eight context models. The 2 × 8 cache allows a performance improvement of 13.2 percent to 16.7 percent compared to a non-cached decoder due to a 17 percent higher clock frequency and highly effective prefetching. The proposed HEVC/H.265 CABAC decoder allows the decoding of high-quality Full HD videos in real-time using few hardware resources on a low-power FPGA.

Context-adaptive variable-length coding

Clock rate

Cache pollution

10.1109/mmul.2017.12

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Citations (9)

Low-Power High-Efficiency Video Decoding using General-Purpose Processors

ACM Transactions on Architecture and Code Optimization (2015)

Chi Bun Ching Mauricio Álvarez-Mesa Ben Juurlink

In this article, we investigate how code optimization techniques and low-power states of general-purpose processors improve the power efficiency of HEVC decoding. The power and performance efficiency of the use of SIMD instructions, multicore architectures, and low-power active and idle states are analyzed in detail for offline video decoding. In addition, the power efficiency of techniques such as “race to idle” and “exploiting slack” with DVFS are evaluated for real-time video decoding. Results show that “exploiting slack” is more power efficient than “race to idle” for all evaluated platforms representing smartphone, tablet, laptop, and desktop computing systems.

Laptop

SIMD

Idle

Electrical efficiency

Multi-core processor

Code (set theory)

10.1145/2685551

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Citations (14)

High performance memory accesses on FPGA-SoCs

Matthias Göbel Chi Bun Ching Mauricio Álvarez-Mesa Ben Juurlink

10.14279/depositonce-5785

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GPU Parallelization of HEVC In-Loop Filters

International Journal of Parallel Programming (2017)

Biao Wang Diego F. de Souza Mauricio Álvarez-Mesa Chi Bun Ching Ben Juurlink

Theory of computation

10.1007/s10766-017-0488-z

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Citations (6)

Reducing HEVC encoding complexity using two-stage motion estimation

Gabriel Cebrián-Márquez Chi Bun Ching José Luis Martínez Pedro Cuenca Mauricio Álvarez-Mesa

We propose a technique for optimizing the High Efficiency Video Coding (HEVC) encoder by reducing the number of operations performed in the motion estimation stage. The technique is based on the fact that a significant number of motion estimation operations are performed repetitively for the same image samples, but for different block partition sizes. By decoupling the initial motion estimation and the block partitioning into different stages it is possible to remove a considerable number of redundant motion estimation operations. An implementation of the proposed technique on a SIMD optimized version of the HEVC reference encoder shows that, on average, a reduction of 79.02% SAD operations can be achieved, that results in an average reduction of 14.63% of the encoding complexity with negligible impact on the compression efficiency (BD-rate losses of less than 1%).

Quarter-pixel motion

Algorithmic efficiency

Decoupling (probability)

10.1109/vcip.2015.7457851

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Citations (6)

Film265: Report on Achieved Quality Improvements: Public Version. Research Data

Mauricio Álvarez-Mesa Sergio Sanz-Rodríguez

EC/H2020/645500/EU/Improving European VoD Creative Industry with High Efficiency Video Delivery/Film265

10.14279/depositonce-5453

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Citations (0)