The concept of percolative channel is essential for understanding statistical variability and reliability in nanoscale transistors. In this paper, the quantitative factors of channel current percolation path (PP) are comprehensively studied in planar and FinFET devices for the first time, with statistical simulations and experimental characterizations. The properly-defined PP parameters are well quantified by the proposed new approach, and extracted from `atomistic' device simulation. The experimental data of random telegraph noise (RTN) is used via the atomic PP model to characterize the underlying channel local current fluctuations and thus to benchmark the PP in reality. Experimental results of extracted PP parameters are consistent with those predicted from simulations, confirming the effectiveness of the proposed approach. The 3D PP in FinFET has different features compared with 2D PP in planar devices, and exhibits additional distortion along Fin-width direction. This work provides a unique framework for deep understanding of "random device physics" and thus is helpful for future nano-device design.
Tunnel FET (TFET) is recognized to be one of the most promising candidates for ultra-low power applications due to its ultra-low off current and high compatibility with CMOS process. However, different from the typical features of MOSFET, some electrical characteristics of TFETs caused by asymmetric device structure and special conduction mechanism may make conventional topologies of circuits no longer applicable. In this paper, it is found that the TFETs stacking will result in severe current degradation behavior, which makes traditional topologies of logic gates may be not applicable. To solve this problem, a set of novel hybrid TFET-MOSFET topologies for standard logic cells are proposed. The proposed designs achieve more than 2 times lower hardware cost and intrinsic delay, and realize up to 4 times lower area-power-delay product (APDP) than that of conventional TFET-based logic circuits. Moreover, the proposed topologies can achieve almost 2 orders of magnitude lower power and up to 34 times lower APDP than that of conventional MOSFET-based logic circuits. The proposed standard logic cells show great superiority for power-constraint applications.
Brain-inspired neuromorphic computing is expected to revolutionize the architecture of conventional digital computers and lead to a new generation of powerful computing paradigms, where memristors with analog resistive switching are considered to be potential solutions for synapses. Here we propose and demonstrate a novel approach to engineering the analog switching linearity in TaOx based memristors, that is, by homogenizing the filament growth/dissolution rate via the introduction of an ion diffusion limiting layer (DLL) at the TiN/TaOx interface. This has effectively mitigated the commonly observed two-regime conductance modulation behavior and led to more uniform filament growth (dissolution) dynamics with time, therefore significantly improving the conductance modulation linearity that is desirable in neuromorphic systems. In addition, the introduction of the DLL also served to reduce the power consumption of the memristor, and important synaptic learning rules in biological brains such as spike timing dependent plasticity were successfully implemented using these optimized devices. This study could provide general implications for continued optimizations of memristor performance for neuromorphic applications, by carefully tuning the dynamics involved in filament growth and dissolution.
A novel self-turnoff control circuit for program process of one-time programmable (OTP) cell is proposed. Utilizing the current turnoff technology after the breakdown of OTP cell, it lowers the power consumption efficiently compared with traditional structures without turnoff mechanism. In addition, an additional delay circuit is also attached to the self-turnoff circuit to ensure the complete breakdown of OTP cell. The simulation results show that the average power consumption of proposed circuit decreases to about 3nA in the whole program process.
In this paper, it was noted that the transient C-t characteristics under high gate voltage was different from the normal one under a lower gate voltage, and that the equilibrium capacitance (C-t) decreased when the applied gate voltage increased. Here, we present a new model that is able to explain the phenomena of a pulsed MOS structure with Fowler-Nordheim tunneling current.
In this paper two kinds of novel localized-SOI structure devices, named as Quasi-SOI MOSFET and source-drain -on-nothing(SDON)/source-drain-on-insulator (SDOI) MOSFET, are demonstrated which can combine the advantages of SOI and bulk substrates. In the Quasi-SOI structure with the source/drain regions quasi-surrounded with insulator and the channel region directly connected with the bulk substrate, short channel effects (SCE), parasitic capacitance and self-heating effects (SHE) can be effectively reduced. The problem of degraded mobility and increased threshold voltage due to ultra-thin body in UTB SOI MOSFET's can also be solved. A method to fabricate the Quasi-SOI MOSFET is put forward. Process-device co-simulation results further show good scaling capability and excellent heat dissipation of the Quasi-SOI devices. In the SDON/SDOI device with the recessed S/D extension regions and source-drain staying on the partially buried layers, the advantages of quasi-SOI MOSFET can be maintained with the parasitic capacitance further reduced and the fabrication technology basically compatible with the standard CMOS technology. The proposed two structures can be considered as good candidates for highly-scaled devices.
A control-gate- (CG) assisted erasing method is investigated for the embedded single-poly EEPROM cell with metallic CG structure. Without the CG bias polarity limitation, which suffers in the diffused n-well CG EEPROM cells, the metallic CG cells can apply negative voltage at CG. By negatively biasing the CG, an enhanced electric field, and thus an improved erasing speed can be achieved for the source erasing. With the channel hot electron (CHE) programming and the enhanced erasing method, an enlarged threshold window can be obtained. In addition, the reliability of the EEPROM cell fabricated with the foundry standard CMOS process with an enhanced erasing method is studied.
A new body-on-insulator (BOI) FinFET device structure based on bulk-Si substrate has been proposed and experimentally demonstrated in this paper. In comparison with other bulk FinFETs, the BOI FinFET features the localized insulator below the Si-Fin body, which can achieve both low source/drain (S/D) parasitic resistance and effective suppression of the S/D leakage beneath the Si-Fin channel, as well as good heat dissipation capability. The device fabrication process is basically compatible with conventional CMOS technology. High drive current, low subthreshold swing, and excellent short-channel behavior are observed in the fabricated BOI FinFETs.
'/%3e%3cuse xlink:href='%23a' transform='rotate(23.036 .093 25.536)'/%3e%3cuse xlink:href='%23a' transform='rotate(45.87 1.273 16.18)'/%3e%3cuse xlink:href='%23a' transform='rotate(69.945 .996 12.078)'/%3e%3cuse xlink:href='%23a' transform='rotate(20.66 -19.689 31.932)'/%3e%3c/svg%3e)
'/%3e%3cuse xlink:href='%23a' transform='rotate(144 450 300)'/%3e%3cuse xlink:href='%23a' transform='rotate(216 450 300)'/%3e%3cuse xlink:href='%23a' transform='rotate(288 450 300)'/%3e%3c/svg%3e)