E. Kiewra

GlobalFoundries (United States)

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Marwan Khater

Benha University

Carol Reinholm

IBM (United States)

Tymon Barwicz

IBM (United States)

Yurii A. Vlasov

University of Illinois Urbana-Champaign

Steven M. Shank

GlobalFoundries (United States)

J. Fompeyrine

IBM Research - Zurich

D. M. Gill

IBM (United States)

Solomon Assefa

IBM (United States)

Yanning Sun

IBM Research - Thomas J. Watson Research Center

Jessie Rosenberg

IBM (United States)

Cooperative Institutions

IBM (United States)

150

IBM Research - Thomas J. Watson Research Center

GlobalFoundries (United States)

IBM Research - Zurich

Infineon Technologies (United States)

Toshiba (United States)

University of California, Santa Barbara

Siemens (Germany)

Massachusetts Institute of Technology

Siemens Healthcare (United States)

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A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications

International Electron Devices Meeting (2012)

Solomon Assefa Steven M. Shank William H. Green Marwan Khater E. Kiewra

The first sub-100nm technology that allows the monolithic integration of optical modulators and germanium photodetectors as features into a current 90nm base high-performance logic technology node is demonstrated. The resulting 90nm CMOS-integrated Nano-Photonics technology node is optimized for analog functionality to yield power-efficient single-die multichannel wavelength-mulitplexed 25Gbps transceivers.

Transceiver

10.1109/iedm.2012.6479162

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Citations (160)

A low redeposition rate high density plasma CVD process for high aspect ratio 175 nm technology and beyond

G.Y. Lee T. Ivers George D. Papasouliotis E. Kiewra Xinghai Ning

As aluminum reactive ion etch (RIE) technology extends to sub-0.20 /spl mu/m technology, a void-free back-end-of-line (BEOL) gap-fill process is one of the major challenges for interconnects. When a stitched word line architecture is employed, the first metal wiring level often follows the minimum ground rule (GR). To maintain low sheet resistance, the aluminum line height cannot be significantly reduced. Therefore, the aspect ratio of current spaces is well over 2.5 and will approach 4.5 with future lithography shrinkages. Deposition temperature constraints make BEOL gap-fill much harder than front-end-of-line (FEOL), where such high aspect ratios are routinely filled. In this paper, a low redeposition rate high density plasma chemical vapor deposition (HDP-CVD) process has been developed at low deposition temperature to fill beyond 3.0 to 1 aspect ratio without void formation.

Void (composites)

Aspect ratio (aeronautics)

10.1109/iitc.1999.787106

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Citations (4)

Influence of sidewall roughness on the reliability of 0.20-μm Al RIE wiring

R.V.S.S.N. Ravikumar H. Cichy R. G. Filippi E. Kiewra D.L. Rath

Aluminum based wiring is widely used in the back-end-of-line (BEOL) metallization of integrated circuits. In a 256 Mb dynamic random access memory (DRAM) product, the first level of Al wiring exists at a 0.20 /spl mu/m ground rule. Performance and reliability issues from these aggressive ground rules result in serious challenges for semiconductor fabrication processing at the BEOL. This paper compares two different sidewall roughness profiles which were created by varying the post-metal etch wet clean. The resulting "rough" and "smooth" sidewall profiles are correlated with the electrical performance and reliability characteristics of the 256 Mb-DRAM product.

Dram

Dynamic random-access memory

Circuit reliability

Semiconductor Industry

10.1109/iitc.1999.787104

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Citations (0)

Distributed electrode Mach-Zehnder modulator with double-pass phase shifters and integrated inductors

Optics Express (2015)

D. M. Gill W. M. J. Green Chi Xiong Alexander Rylyakov Clint L. Schow

A novel high-speed Mach-Zehnder modulator (MZM) fully integrated into a 90 nm CMOS process is presented. The MZM features 'double-pass' optical phase shifter segments, and the first use of integrated inductors in a 'velocity-matched' distributed-electrode configuration.

Phase shift module

Electro-optic modulator

10.1364/oe.23.016857

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Citations (9)

New Aqueous Clean for Aluminum Interconnects: Part I. Fundamentals

Diffusion and defect data, solid state data. Part B, Solid state phenomena/Solid state phenomena (2001)

D.L. Rath R.V.S.S.N. Ravikumar D.J. Delehanty R. G. Filippi E. Kiewra

10.4028/www.scientific.net/ssp.76-77.31

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Citations (6)

Monolithic Silicon Photonic WDM Transceivers

Jessie Rosenberg Folkert Horst Marwan Khater Frederick G Anderson Robert Leidy

Monolithic silicon photonic technology provides high bandwidth and large volume for datacom applications, while maintaining the low-cost assembly and waferscale test readiness characteristic of CMOS. Monolithic integration and high-yield CMOS processing enables complex, high-performance WDM architectures for CWDM4 transceivers.

Transceiver

10.1109/ecoc.2017.8346134

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Citations (4)

A linear push-pull silicon optical modulator

Frontiers in Optics (2014)

Chi Xiong D. M. Gill Jessie Rosenberg Marwan Khater Tymon Barwicz

We present a linear push-pull driven silicon modulator fabricated in IBM's CMOS9WG technology node. The Si modulator shows third order nonlinearity suppression 3 dB superior in comparison with a commercial lithium niobate modulator.

Modulation (music)

10.1364/fio.2014.fm3a.4

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Citations (6)

Sputtering Behavior and Evolution of Depth Resolution upon Low Energy Ion Irradiation of GaAs

ECS Transactions (2010)

Marinus Hopstaken Dirk Pfeiffer Michael Gordon E. Kiewra Yanning Sun

We investigate the sputtering behavior and depth resolution upon low energy ion irradiation during Secondary Ion Mass Spectrometry (SIMS) depth profiling of GaAs. We present a systematic and quantitative study of the impact of ion species, primary ion impact energy, and incident angle on the evolution of depth resolution, using a well-defined InGaAs/GaAs multilayer structure with highly abrupt hetero-interfaces. We demonstrate that for low energy O2+ ion beam irradiation, SIMS depth resolution becomes progressively degraded by (transient) incorporation of high surface O-concentration levels in the altered layer, leading to detrimental ion-beam induced formation of topography. In case of low energy oblique Cs+ ion beam irradiation, sputtering behavior of GaAs is well-behaved with no significant transient yield changes and a constant depth resolution. This enables SIMS depth profiling of sharp hetero-epitaxial III-V compound semiconductor structures and shallow dopant profiles with sufficiently good depth resolution with good detection efficiency.

10.1149/1.3367952

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Citations (1)

Silicon photonics and challenges for fabrication

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE (2017)

N. Feilchenfeld Karen Nummy Tymon Barwicz D. M. Gill E. Kiewra

Silicon photonics is rapidly becoming the key enabler for meeting the future data speed and volume required by the Internet of Things. A stable manufacturing process is needed to deliver cost and yield expectations to the technology marketplace. We present the key challenges and technical results from both 200mm and 300mm facilities for a silicon photonics fabrication process which includes monolithic integration with CMOS. This includes waveguide patterning, optical proximity correction for photonic devices, silicon thickness uniformity and thick material patterning for passive fiber to waveguide alignment. The device and process metrics show that the transfer of the silicon photonics process from 200mm to 300mm will provide a stable high volume manufacturing platform for silicon photonics designs.

Waveguide

Hybrid silicon laser

10.1117/12.2263472

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Citations (18)

High mobility III–V channel MOSFETs for post-Si CMOS applications

Yanning Sun E. Kiewra J. P. de Souza Steven J. Koester J. J. Bucchignano

III-V compound semiconductors have received renewed attention as the channel materials for future generation CMOS technology. High performance long-channel GaAs MOSFETs and short-channel InGaAs MOSFETs are demonstrated. High current of 960 muA/mum and transconductance of 793 muS/mum have been achieved. Scaling behavior has been investigated experimentally down to 80 nm for the first time in III-V MOSFETs. Good scaling behavior is observed for on-state current, transconductance, as well as the virtual source velocity.

Transconductance

Electron Mobility

10.1109/icicdt.2009.5166286

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Citations (1)