X. Li

University of Glasgow

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Iain Thayne

University of Glasgow

Haiping Zhou

University of Electronic Science and Technology of China

Richard J. Hill

Fermi National Accelerator Laboratory

S. Thoms

University of Glasgow

M. Passlack

Taiwan Semiconductor Manufacturing Company (United States)

David A. J. Moran

University of Glasgow

K. Elgaid

Cardiff University

Ravi Droopad

Texas State University

Ivor Guiney

University of Cambridge

Abdalla Eblabla

Cardiff University

Cooperative Institutions

University of Glasgow

Taiwan Semiconductor Manufacturing Company (Taiwan)

Motorola (United States)

Cardiff University

Texas State University

Imperial College London

University of Edinburgh

KU Leuven

ON Semiconductor (United States)

University of Oxford

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Low-Loss MMICs Viable Transmission Media for GaN-on-Low Resistivity Silicon Technology

IEEE Microwave and Wireless Components Letters (2016)

Abdalla Eblabla Bhavana Benakaprasad X. Li D. J. Wallis Ivor Guiney

In this work a novel ultra-low loss transmission media for RF GaN-on-low-resistivity silicon (LR-Si) substrates (σ <; 40 Ω.cm) has been successfully demonstrated. The developed shielded-microstrip lines achieve comparable performance to those on semi-insulating (SI) GaAs substrates with transmission loss of 0.9 dB/mm for frequencies up to 67 GHz. Line performance was further enhanced by additional elevation of the shielded-microstrip lines using air-bridge technology above a 5 μm layer of benzocyclobutene (BCB) on shielded metalized ground planes. Transmission loss of 0.6 dB/mm for frequencies up to 67 GHz was obtained as a result of the extra elevation. Structure parameters were designed and optimized based on EM simulation for best performance. The work shows that the RF energy coupled into the substrate was eliminated, indicating the suitability of III-V-on-LR Si technology for millimeter-wave applications.

Shielded cable

Benzocyclobutene

Return loss

10.1109/lmwc.2016.2629964

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Citations (7)

Direct nanopatterning of commercially pure titanium with ultra-nanocrystalline diamond stamps

physica status solidi (a) (2012)

Andrew I. M. Greer K. Seunarine Ali Z. Khokhar X. Li David A. J. Moran

In order to directly imprint features into a hard metal such as titanium, an imprinting stamp composed of material of greater hardness is required. Diamond is the hardest known material, so is an obvious choice for the production of direct-imprint stamps. Diamond also benefits from a low surface energy, chemical inertness, high resistance to wear and is easily cleaned of contaminants, further favouring it as a stamp material of choice. Chemical vapour deposited ultra-nanocrystalline diamond (UNCD) provides similar mechanical properties to bulk single crystal diamond and can be deposited across large surface areas. This work examines the use of UNCD as a stamp medium for the transfer of nanoscale features into commercially pure titanium (cpTi) substrates. Development of an efficient and viable method for nanopatterning large, non-planar cpTi surfaces is highly desirable to control cell adhesion on the surface of bio-implants. The fabrication of UNCD nanoimprint stamps is detailed and the ability of UNCD to imprint cpTi is illustrated. A square-ordered matrix of 200 nm diameter pillars over a quarter mm square area are shown to be imprinted with the depth quantified against load (kg). The limitations of the technology are also discussed.

Diamond cutting

10.1002/pssa.201200057

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Citations (9)

Deep sub-micron and self-aligned flatband III–V MOSFETs

Device Research Conference (2009)

Richard J. Hill X. Li Haiping Zhou D.S. Macintyre S. Thoms

In conclusion, this paper reports a number of significant developments in III-V MOSFET devices. Retaining a subthreshold slope of 60-70 mV/decade for gate lengths down to 100 nm with an EOT of 3.4 nm shows for the first time that the flatband mode device architecture is tolerant to short channel effects. In addition, a generic silicon compatible process flow for the realization of fully self-aligned III-V MOSFETs has been demonstrated and shown capable of realizing 100 nm gate length enhancement mode devices.

Subthreshold slope

Subthreshold conduction

Realization (probability)

10.1109/drc.2009.5354900

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Citations (2)

1 [micro sign]m gate length, In0.75Ga0.25As channel, thin body n-MOSFET on InP substrate with transconductance of 737 [micro sign]S/μm

Electronics Letters (2008)

Richard J. Hill Ravi Droopad David A. J. Moran X. Li Haiping Zhou

The first demonstration of implant-free, flatband-mode In0.75Ga0.25As channel n-MOSFETs is reported. These 1 µm gate length MOSFETs, fabricated on a structure with average mobility of 7720 cm2/Vs and sheet carrier concentration of 3.3×1012 cm−2, utilise a Pt gate, a high-κ dielectric (κ≃20), and a δ-doped InAlAs/InGaAs/InAlAs heterostructure. The devices have a typical maximum drive current (Id,sat) of 933 µA/µm, extrinsic transconductance (gm) of 737 µS/µm, gate leakage (Ig) of 40 pA, and on-resistance (Ron) of 555 Ω · µm. The gm and Ron figures of merit are the best reported to date for any III-V MOSFET.

Transconductance

10.1049/el:20080470

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Citations (26)

High-Performance MMIC Inductors for GaN-on-Low-Resistivity Silicon for Microwave Applications

IEEE Microwave and Wireless Components Letters (2018)

Abdalla Eblabla X. Li D. J. Wallis Ivor Guiney K. Elgaid

Novel MMIC spiral inductors on GaN-on-low-resistivity silicon (LR-Si) substrates (σ <; 40 Ω · cm) are demonstrated with enhanced self-resonance frequency ( fSRF) and Q-factor. The developed technology improves inductor performance by suppressing substrate coupling effects using air-bridge technology above benzocyclobutene dielectric as an interface layer on the lossy substrate. A 0.83-nH spiral inductor with peak Q-factor enhancement of 57% (Q = 22 at 24 GHz) and maximum fSRF of 59 GHz was achieved because of the extra 5-μm elevation in air. An accurate broad-band model for the fabricated inductors has been developed and verified for further performance analysis up to 40 GHz. The proposed inductors utilize cost-effective, reliable, and MMIC-compatible technology for the realization of high-performance RF GaN-on-LR Si MMIC circuits for millimeter-wave applications.

Q factor

Benzocyclobutene

10.1109/lmwc.2018.2790705

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Citations (12)

Surface mass spectrometric analysis of SiCl4/SiF4/O2 dry etch gate recessed 120nm T-gate GaAs pHEMTs

Microelectronic Engineering (2005)

X. Li K. Elgaid H. McLelland I.G. Thayne

Dry etching

10.1016/j.mee.2004.12.032

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Citations (0)

High Aspect Ratio Junctionless InGaAs FinFETs Fabricated Using a Top-Down Approach

David Alan John Millar X. Li Uthayasankaran Peralagu Matthew J. Steer I.M. Pavey

The junctionless MOSFET (JLFET) architecture has attracted much attention as an enabling technology for ultra-scaled CMOS devices [1]. The dominant scattering mechanism in JLFETs is impurity scattering due to its necessarily highly doped channel [1]. Accordingly, III-V's may offer an even greater advantage as the channel material for JLFETs than for conventional MOSFETs as they suffer less from mobility degradation due to impurity scattering [2]. Current Si CMOS devices employ non-planar architectures with high aspect ratio fins which serve to increase the on current (Ion) per chip surface area [3]. This necessitates that any incarnation of a III - V MOSFET must also exploit the vertical dimension. Additionally, it must do so by employing a `top-down' fabrication approach to remain compatible with Si CMOS processing. This requires a low Dit dielectric interface to etched III-V fin sidewalls. To date, all III-V junctionless FinFETs (JLFinFETs) demonstrated have employed fin heights which are smaller than the maximum depletion width of their respective channels, and therefore can be well modulated by the top gate only: offering little insight into the effectiveness of the gated sidewalls. We implement a low damage etch process to form high aspect ratio, In053Ga047As JLFinFETs which have record performance in terms of Ion normalized to fin width.

Aspect ratio (aeronautics)

Fin

10.1109/drc.2018.8442150

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Citations (2)

InAs FinFETs With H_finnm Fabricated Using a Top–Down Etch Process

IEEE Electron Device Letters (2016)

R. Oxland X. Li S. W. Chang S. W. Wang T. Vasen

We report the first demonstration of InAs FinFETs with fin width W fin in the range 25-35 nm, formed by inductively coupled plasma etching.The channel comprises defect-free, lattice-matched InAs with fin height H fin = 20 nm controlled by the use of an etch stop layer incorporated into the device heterostructure.For a gate length L g = 1 µm, peak transconductance g m,peak = 1430 µS/µm is measured at V d = 0.5 V demonstrating that electron transport in InAs fins can match planar devices.

10.1109/led.2016.2521001

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Citations (24)

High Performance GaN High Electron Mobility Transistors on Low Resistivity Silicon for <inline-formula> <tex-math notation="LaTeX">$X$ </tex-math></inline-formula>-Band Applications

IEEE Electron Device Letters (2015)

Abdalla Eblabla X. Li Iain Thayne D. J. Wallis Ivor Guiney

This letter reports the RF performance of a 0.3-μm gate length AlGaN/AlN/GaN HEMT realized on a 150-mm diameter low-resistivity (LR) (σ <; 10 Ω · cm) silicon substrate. Short circuit current gain (f _T ) and maximum frequency of oscillation (f _MAX ) of 55 and 121 GHz, respectively, were obtained. To our knowledge, these are the highest f _T /f _MAX values reported to date for GaN HEMTs on LR silicon substrates.

10.1109/led.2015.2460120

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Citations (28)

Two methods of realising 10 nm T-gate lithography

Microelectronic Engineering (2008)

Steven Bentley X. Li David A. J. Moran Iain Thayne

Dry etching

10.1016/j.mee.2008.12.029

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Citations (10)