Bruce Hu

Semiconductor Manufacturing International (Italy)

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Andy Tseng

ON Semiconductor (United States)

Yi‐Shao Lai

Advanced Semiconductor Engineering (Taiwan)

Mark W. Lin

University of Alabama in Huntsville

Sunny Lee

Advanced Semiconductor Engineering (Taiwan)

Ji Tang

JM Wan

Advanced Semiconductor Engineering (Taiwan)

Chenyu Wang

Southwest University

Peng Li

Ministry of Industry and Information Technology

Bill C.J.

Advanced Semiconductor Engineering (Taiwan)

JW Chen

Zhongkai University of Agriculture and Engineering

Cooperative Institutions

Advanced Semiconductor Engineering (Taiwan)

ON Semiconductor (United States)

National Taipei University of Technology

Evans Analytical Group (United States)

Tatung University

American Society of Mechanical Engineers

I-Shou University

Quality and Reliability (Greece)

The University of Texas at Austin

National Central University

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Advanced QFN packaging for low cost and solution

Bill C.J.Bruce Hu Mark W. Lin Timmy Lin Sunny Lee

The advanced QFN (aQFN) package is an enhanced version of conventional QFN (Quad Flat No-Lead) with multiple row terminals of featuring higher number of I/O ports. aQFN thermal and electrical performance are superior due to smaller profile, shorter interconnects. Also, the solder wettability control and board-level thermo-mechanical reliability are greatly enhanced over conventional QFN because of the higher package standoff. aQFN provides similar I/O number approaching that of a BGA-type chip-scale package (CSP) but much less cost since the expensive substrate is replaced by lead frame. aQFN turns out to be an ideal low cost solution for electrical components of portable telecommunication applications. With such advantages, the replacement of BGA-type CSP with aQFN from low pin-count up to medium high pin-count applications is therefore highly expectable, especially for handheld & PDA devices with its relative applications. In this paper, aQFN is introduced in terms of its application advantages, development, fabrication process flow, SMT process with stencil design guideline. The simulation results indicate that thermal and electrical performances of aQFN are much better than BGA-type CSP, when the same functions are to be designed in SMT process.

Ball grid array

Lead frame

Chip-scale package

Stencil

Integrated circuit packaging

Package on package

Electronic Packaging

Temperature cycling

10.1109/icept.2010.5582373

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Citations (15)

Advanced QFN Surface Mount Application Notes development

Andy Tseng Mark W. Lin Bruce Hu JW Chen JM Wan

The advanced Quad Flat No-Lead (aQFN) package is an enhanced version of conventional QFN with multiple row terminals of featuring higher number of I/O ports. The aQFN thermal and electrical performance are superior due to smaller profile and shorter interconnects and the solder wettability control and board-level thermo-mechanical reliability are greatly enhanced over conventional QFN because of the higher package standoff. aQFN provides similar I/O number approaching that of a BGA-type chip-scale package (FBGA) but much less cost since the expensive substrate is replaced by lead frame. aQFN turns out to be an ideal low cost solution for electrical components of portable telecommunication applications such as IrDA, blue-tooth, RFID, cell phone baseband etc. for its superior thermal, electrical, reliability performances and miniaturized package size, With such advantages, the replacement of FBGA with aQFN in low up to medium lead-count applications is therefore highly expectable, especially for handheld & PDA devices with its related applications. With such higher pin-count, multi-row and small terminal pitch than QFN, how to design the aQFN package terminals for printed circuit board layout and the stencil patterning and opening for solder paste printing become crucial issues. aQFN will be introduced in terms of its application advantages, development, fabrication process flow, SMT process with stencil design guideline for surface mount assembly yield. Finally, "Surface Mount Application Notes" have been issued.

Mount

Surface-mount technology

10.1109/eptc.2010.5702735

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Citations (10)

EPI Surface Particle Reduction on NROM Word Line Application

ECS Transactions (2012)

Hezhen Yang Ji Tang Chenyu Wang David Li Bruce Hu

Epitaxy (Epi) technology is widely used for Logic, DRAM and Flash memory process in semiconductor manufacturing industry. Reduced pressure Epi chamber of Applied Materials applied for NROM Flash memory application is introduced, and particle issue occurred during Word Line poly-silicon deposition process is solved.

Dram

Particle (ecology)

Line (geometry)

Deposition

Semiconductor device fabrication

10.1149/1.3694309

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