A new, cost effective, robust high voltage device without epitaxial layer for HVIC, is proposed. The P-TOP layer is introduced to reduce on-resistance while maintaining the breakdown voltage of over 700V for LDMOS and JFET. Also, this paper presents the design concept and device structure of source corner region without additional mask layer and loss of channel (HNWELL) for RESURF condition. We achieved that the breakdown voltage of proposed JFET is over 750V with Vpinch=30V and DR-LDMOS is lower ~ 7% lower on-resistance than conventional type (cut-out of HVNWELL).
We have developed nLDMOS with over 800V BV based on 0.35㎛ technology using Double RESURF (REduced SURface Field) technology without extra layers & Epi wafer. This device is applied to power switch and level shifter for HVIC such as LED lighting, motor control IC, etc. Also, this paper presents the optimization condition for wide RESURF region regarding a robust breakdown voltage and low specific on-resistance
We proposed the new process flow that is P-body region formation after gate etch using DPP(Double PR Process) for improving Rsp and stable Vt of nLDMOS. The performance is achieved to reduce about 30% specific on-resistance without sacrificing the BVdss and additional process. The result is dramatically reduction of chip size regarding improvement of Rsp..
In this paper, two kinds of robust 700V DR-LDMOS (Double RESURF LDMOS) using thin epitaxial technology has been realized for level shifter and switching applications. The P-TOP layer is introduced to reduce on-resistance while maintaining high breakdown voltage for switching applications, and to increase on-breakdown voltage using JFET resistance for level shifter. The result is that the breakdown voltage of the 700V LDMOS for level shifter is 900V with on-breakdown of over 650V. In terms of switching applications, we have adopted HVPWELL layer of rainbow shape at source corner region to reduce n-type charge of N-EPI region and achieved the breakdown voltage of over 750V.
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