S. Note

IMEC

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Citation

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i-10 index

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Co-Authors

Francky Catthoor

IMEC

H. De Man

University College London

Gert Goossens

Synopsys (Belgium)

J. van Meerbergen

Philips (Netherlands)

D. Lanneer

Synopsys (Belgium)

Jan Vanhoof

University of Antwerp

P. Vandebroek

Philips (Belgium)

Luc Van Eycken

KU Leuven

J.L. van Meerbergen

Eindhoven University of Technology

H. De Man

IMEC

Cooperative Institutions

KU Leuven

IMEC

Philips (Netherlands)

Imec the Netherlands

NXP (Netherlands)

Philips (Finland)

Philips (Belgium)

International Medical Equipment Collaborative

Eindhoven University of Technology

Philips (Spain)

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A single battery, 0.9 V operated digital sound processing IC including AD/DA and IR receiver with 2 mW power consumption

H. Neuteboom M. Janssens J.R.G.M. Leenen B.M.J. Kup E.C. Dijkmans

The sound processing on this chip is done digitally by a programmable DSP processor. The sound processing algorithms are stored in an on-chip RAM. A new algorithm can be downloaded into the RAM through an infrared (IR) remote control. The onboard A/D and D/A converter and IR receiver make this chip a complete stand alone system, needing only a battery, a microphone and/or telecoil, an earphone, an IR diode and few external components. Applications are in hearing instruments and related products. The chip is supplied by a single 1.3V battery, runs at 1MHz clock frequency and consumes only 2mW in full functional mode. The audio sample rate is 16kHz. The dynamic ranges of the A/D and D/A converter (including digital filters, noise shaper and output amplifiers) are 80dBA and 93dBA respectively. The THD of the overall signal path is better than -45dB. The chip is manufactured in a standard low-threshold 0.8/spl mu/m CMOS process.

10.1109/isscc.1997.585279

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Citations (8)

A methodology for performance driven data-path compilation

S. Note Francky Catthoor Gert Goossens H. De Man

In this paper, a methodology is described for performance driven compilation of data-paths suited for high throughput real time DSP applications. The emphasis lies on the designers point of view, i.e. on the effect of the different performance optimizations, and the sequence in which to apply them. The resulting methodology has been implemented in a tool called Chopin.< >

Sequence (biology)

Emphasis (telecommunications)

10.1109/easic.1990.207925

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Citations (5)

Real-time emulation of DSP applications on programmable DSPs and FPGAs

Rudy Lauwereins M. Adé S. Note

The paper describes the RETIDES design flow and building blocks which allow for fast and cost-effective prototyping of complete DSP systems on heterogeneous re-usable hardware platforms consisting of general purpose DSP processors, core processors and field programmable gate arrays. Early experiences with two classes of industrial audio and speech applications are reported.

USable

Design flow

Rapid Prototyping

Hardware emulation

10.1109/icecs.1996.582928

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Citations (0)

Combined hardware selection and pipelining in high performance data-path design

S. Note Francky Catthoor Gert Goossens H. De Man

Pipelining and hardware selection are important optimization tasks in the design of high-performance data paths. At the highest abstraction level, the specification of a data path consists of a number of interconnected abstract building blocks and a constraint on the minimal required clock frequency. An algorithm which optimally selects hardware blocks from a library for implementing these abstract building blocks is presented, and a technique for hierarchical redistribution and insertion of pipeline registers is described. Finally, both optimization tasks are combined. This combination makes the area tradeoff between additional speed-up circuitry and pipeline registers possible.< >

Abstraction

High-Level Synthesis

10.1109/iccd.1990.130241

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Citations (14)

Architectural synthesis for medium and high throughput signal processing with the new Cathedral environment

Springer eBooks (1991)

D. Lanneer S. Note Francis Depuydt Marc Pauwels Francky Catthoor

Application-specific integrated circuit

Bridge (graph theory)

Realisation

SIGNAL (programming language)

10.1007/978-1-4615-3966-7_2

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Citations (31)

Automatic synthesis of signal processing benchmark using the CATHEDRAL silicon compilers

Luc Claesen Francky Catthoor D. Lanneer G. Goosens S. Note

A discussion is presented of implementation of two WDF (wave digital filter) benchmarks that have been designed with three architecture-specific silicon compilers. The design time for high-level synthesis and optimization is roughly one day. For each of the three synthesis systems, the elapsed design cycle starting from the specifications down to the optimized signal flow graph is another 1-2 days. For the architecture and layout generation (including the evaluation of the tradeoffs), the design time ranges from a few hours to a day. Specific higher-level filter specifications have been used for the synthesis with three different implementation strategies in the CATHEDRAL silicon compilers. It is shown that as an initial optimization step, it is important to initially choose a good algorithm.< >

Benchmark (surveying)

Signal-flow graph

High-Level Synthesis

SIGNAL (programming language)

10.1109/cicc.1988.20869

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Citations (30)

Application of advanced DSP tools for the design of an IC for Digital European Cordless Telephone systems

S. Note P. Vandebroek D. Devisch

The authors describes the design of a digital telecommunication chip to be used in Digital European Cordless Telephone systems (DECT). The focus is on the algorithmic design and optimization of the A/D and D/A processing path, and on the architecture design process. The complete design has been performed using the DSP Station environment.< >

Cordless

Design process

10.1109/vlsisp.1993.404494

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Citations (1)

Definition and assignment of complex data-paths suited for high throughput applications

S. Note Francky Catthoor J. van Meerbergen H. De Man

A novel methodology is proposed for the data-path definition and assignment for high-throughput front-end audio, image, and video applications. The technique is based on the concept of the identification of application-specific units that can solve the computational bottlenecks of an algorithm in an efficient way. An algorithm for the automatic assignment of operations on these specific units is presented. A test vehicle taken from the video field demonstrates the proposed method.< >

Identification

10.1109/iccad.1989.76915

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Citations (31)

A data path layout assembler for high performance DSP circuits

Hongping Cai S. Note P. Six H. De Man

A system is presented which automatically generates layout of bit-sliced data paths in high performance DSP circuits. The system consists of a linear placement tool, a track assignment tool and detailed layout tools. In this paper we will present algorithms for linear placement of modules and routing track assignment across the modules. By taking advantage of the inherent structure of the circuits an A* based linear placement algorithm has produced better results compared to a simulated annealing based approach.

Placement

Place and route

Integrated circuit layout

10.1145/123186.123284

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Citations (23)

Cathedral-III

S. Note Werner Geurts Francky Catthoor Hugo De Man

Article Free Access Share on Cathedral-III: Architecture-driven high-level synthesis for high throughput DSP applications Authors: Stefaan Note IMEC Laboratory, Kapeldreef 75, B-3001 Leuven, Belgium IMEC Laboratory, Kapeldreef 75, B-3001 Leuven, BelgiumView Profile , Werner Geurts IMEC Laboratory, Kapeldreef 75, B-3001 Leuven, Belgium IMEC Laboratory, Kapeldreef 75, B-3001 Leuven, BelgiumView Profile , Francky Catthoor IMEC Laboratory, Kapeldreef 75, B-3001 Leuven, Belgium and ESAT Laboratory, Katholieke Universiteit, K. Mercierlaan 94, B-3001 Leuven, Belgium IMEC Laboratory, Kapeldreef 75, B-3001 Leuven, Belgium and ESAT Laboratory, Katholieke Universiteit, K. Mercierlaan 94, B-3001 Leuven, BelgiumView Profile , Hugo De Man IMEC Laboratory, Kapeldreef 75, B-3001 Leuven, Belgium and ESAT Laboratory, Katholieke Universiteit, K. Mercierlaan 94, B-3001 Leuven, Belgium IMEC Laboratory, Kapeldreef 75, B-3001 Leuven, Belgium and ESAT Laboratory, Katholieke Universiteit, K. Mercierlaan 94, B-3001 Leuven, BelgiumView Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 597–602https://doi.org/10.1145/127601.127739Online:01 June 1991Publication History 99citation354DownloadsMetricsTotal Citations99Total Downloads354Last 12 Months8Last 6 weeks3 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

10.1145/127601.127739

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Citations (123)