Abstract The co-packaging of optics and electronics provides a potential path forward to achieving Pbps per package data capacities. In a co-packaged design, the scaling of bandwidth, cost, and energy is governed by the number of optical tranceivers per package as opposed to transistor shrink. The scaling of optical transceivers is hindered by the need to actively assemble bulky single mode fiber arrays directly to optical transceivers. The development of efficient, dense optical couplers with wide alignment tolerances allowing for automated, passive assembly will be an enabler for continued scaling in co-packaged designs. To this end, a passively assembled substrate-to-die evanescent coupler between silicon nitride and silicon was experimentally demonstrated with a 0.39 ± 1.06 dB coupling loss at 1550 nm, a 160 nm 1-dB wavelength tolerance (1480–1640 nm), and a 1-dB lateral alignment tolerance of ± 1.56 μm. The thermal stability was evaluated from 23–60°C with average coupling loss and alignment tolerance varying by less than ± 0.35 dB and ± 30 nm, respectively. Finally, repeatability was evaluated across four packaged systems, demonstrating a coupling loss range of 1.5 dB. Together, these results show this coupler can help achieve Pbps co-packaged optics input/output (I/O) within a sustainable envelope.
Photonics has been one of the primary beneficiaries of advanced silicon manufacturing. By leveraging on mature complementary metal-oxide-semiconductor (CMOS) process nodes, unprecedented device uniformities and scalability have been achieved at low costs. However, some functionalities, such as optical memory, Pockels modulation, and magnetooptical activity, are challenging or impossible to acquire on group-IV materials alone. Heterogeneous integration promises to expand the range of capabilities within silicon photonics. Existing heterogeneous integration protocols are nonetheless not compatible with active silicon processes offered at most photonic foundries. In this work, we propose a novel heterogeneous integration platform that will enable wafer-scale, multi-material integration with active silicon-based photonics, requiring zero-change to existing foundry process. Furthermore, the platform will also pave the way to a class of high-performance devices. We propose a grating coupler design with peak coupling efficiency reaching 93%, an antenna with peak diffraction efficiency in excess of 97%, and a broadband adiabatic polarization rotator with conversion efficiency exceeding 99%.
Chalcogenide optical phase change materials (PCMs) have garnered significant interest for their growing applications in programmable photonics, optical analog computing, active metasurfaces, and beyond. Limited endurance or cycling lifetime is however increasingly becoming a bottleneck toward their practical deployment for these applications. To address this issue, we performed a systematic study elucidating the cycling failure mechanisms of Ge$_2$Sb$_2$Se$_4$Te (GSST), a common optical PCM tailored for infrared photonic applications, in an electrothermal switching configuration commensurate with their applications in on-chip photonic devices. We further propose a set of design rules building on insights into the failure mechanisms, and successfully implemented them to boost the endurance of the GSST device to over 67,000 cycles.
Contemporary silicon photonic heterogeneous integration has indicated a series of challenges. Through the strategic consolidation of foundry-level silicon photonics, and hybrid Cu bonding techniques, we propose SuMMIT, where wafer-scale multi-material integration challenges can be overcome.
Abstract Chalcogenide optical phase change materials (PCMs) have garnered significant interest for their growing applications in programmable photonics, optical analog computing, active metasurfaces, and beyond. Limited endurance or cycling lifetime is however increasingly becoming a bottleneck toward their practical deployment for these applications. To address this issue, a systematic study elucidating the cycling failure mechanisms of Ge 2 Sb 2 Se 4 Te (GSST) is performed, a common optical PCM tailored for infrared photonic applications, in an electrothermal switching configuration commensurate with their applications in on‐chip photonic devices. Further a set of design rules building on insights into the failure mechanisms is proposed, and successfully implemented them to boost the endurance of the Ge 2 Sb 2 Se 4 Te (GSST) device to over 67 000 cycles.
Packaging of photonic integrated circuit (PIC) chips is an essential and critical step before they can be integrated into functional optoelectronic systems. Photonic packaging is however often a major barrier impeding scalable deployment of PIC technologies given its high cost and limited throughput. This perspective addresses the technical challenges and discusses promising strategies and research directions to overcome the "packaging bottleneck".
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