Over the last decade the use of SMT has rapidly replaced through hole component mounting technology. The lead pitch of these surface mounted components has been driven down by the higher pin counts of increasingly complex IC's and by the miniaturisation of electronics systems for portable systems. This push to finer pitch/higher density I/O has meant a revolution in conventional joining and the development of new generations of technology. In this context the authors discuss the properties and use of conductive adhesive materials.
We report on a mechanical characterization technique for individual Ni∕Au coated microsize polymer particles. This technique allows a clearer understanding of the effects of load force and rate on the particle deformation. This has been achieved through measurements of the deformation against force using a specially configured nanoindenter machine, where the “indenters,” instead of being pointed, had a flat tip of 20μm in diameter. The results show that the particle deformation process is nonlinear and that the force/deformation at which particle crushing occurs is affected by the load rate. The technique could be used to design/manufacture more effective conductive particles.
The past few decades have seen an escalation of power densities in electronic devices, and in particular in microprocessor chips. Together with the continuing trend of reduction in device dimensions this has led to dramatic increase in the thermal issues within electronic circuits. Thermal management is therefore becoming increasingly more critical and fundamental to ensuring that electronic devices operate within their specification. Although a thermal management system may make use of all modes of heat transfer to maintain temperatures within their appropriate limits and to ensure optimum performance and reliability, conductive heat transfer is typically used to spread the heat out from its point of generation and into the extended surface area of a heat sink. To minimise the contact resistance, thermal interface materials (TIMs) are introduced to the joint to fill the air gaps and are an essential part of an assembly when solid surfaces are attached together. This paper reviews the conventional interface materials and then goes on to present a comprehensive review of the emerging state-of-the-art research in the use of carbon nanotube based materials. The paper also outlines the advantages and disadvantages of each TIM category and the factors that need to be considered when selecting an interface material
As the demand for flip-chip products increases, the need for high volume, low cost manufacturing processes also increases. All technology roadmaps point towards higher performance products based on finer pitch, high I/O count components. These requirements will push existing low cost solder bumping technologies to their practical limits and future products may have to use higher cost, lower throughput production strategies to achieve the requisite feature sizes. Currently, solder paste printing is the solder deposition method of choice for device pitches down to 150-200 /spl mu/m; however, limitations in print quality and solder paste volume mean that this technology is not likely to move significantly below this pitch. The attractiveness of solder paste printing as a deposition technique due to its low cost and established infrastructure mean that methods for extending its application beyond 150 /spl mu/m pitch would be desirable. This paper describes experiments conducted on carriers made from silicon for bumping of die using solder paste. An anisotropic etching process was used to generate pockets in the silicon surface into which solder paste was printed. Die were then placed against the carrier and reflowed to transfer the solder directly to the bond pads. An assessment was carried out of the potential application and limitations of this technique for device pitches at 225 and 127 /spl mu/m. This was based on experimental observations and model calculations of the efficiency with which the Si carrier apertures could be filled with solder paste.
This paper presents a method for exploring the changes occurring at the surfaces of solder particles during the reflow soldering process. The method involves measuring changes in electrical resistance of a sample of paste as a function of test voltage. The results are used to estimate the size and nature of electrical contact spots between the particles, and how these depend on temperature and time. The activation energy of the process responsible for increasing the size of contact spots is deduced for RA and RMA type fluxes and it is shown that sintering is not the dominant mechanism for increasing contact size. These results, together with a programme of CFD studies are expected to help improve solder paste formulations.
A penetration limit has been experimentally demonstrated for inkjet etching of holes in thin polymer layers. A mechanism combining the competing coffee ring flow, polymer dissolution and diffusion into the solvent drop, and the interaction between the contact line during evaporation and the softened deformable polymer, is proposed to explain the existence of such a penetration limit. The height-averaged velocity of the coffee ring flow within the evaporating sessile drop is calculated during the initial stage of this etching process when the spherical cap geometry assumption is valid. This is compared with the diffusion velocity of the disentangled polymer into the solvent. The two competing flows are used to elucidate why a hole could be formed initially. The complex wetting dynamics of the receding contact line is included to explain the via hole profile evolution in the later stage of the etching process and the existence of a penetration limit. These two stages are differentiated by the drop volume with respect to the volume of the via hole produced by the preceding drop. The competition between the coffee ring flow transferring polymer away from the central region and the polymer diffusion within the solvent drop is postulated to contribute to either via hole formation or a penetration limit, depending on which one of the two processes is dominant within the solvent evaporation time scale.
Conformal coatings are widely used on circuit board assemblies as an attempt to improve reliability and to ensure high insulation impedances, which are for example demanded by low current consumption battery operated RF circuitry. However, components, such as small ceramic capacitors, have occasionally been found to fail in some applications, particularly when covered with a thick silicone conformal coating. This is thought to be due to the diffusion of water through the coating to the capacitor surface where it then combines with solder flux residue, or other organic or ionic contamination left on the components, thereby dramatically increasing the effective component leakage current. The primary objective of this experimental research is therefore to establish a clear understanding of the effects of moisture exposure on the surface insulation resistance (SIR) of conformally coated printed circuit board (PCB) assemblies. This has been achieved through leakage current measurements on multilayer ceramic capacitors during storage in an environmental chamber during testing similar to IPC standards for non-component loaded boards.
Although plastic packaging has successfully replaced ceramic and metal packages for many high reliability electronic packaging applications (e.g. military and aerospace), hermetically sealed ceramic packages are still the dominant technology for large power devices, such as the thyristors and diodes used in high voltage DC (HVDC) power transmission. With increasing energy requirements of growing economies, the demand for higher operating currents is driving suppliers to use larger diameter silicon devices, therefore requiring bigger and more expensive packages. A switch to polymer packaging in such applications has the potential to provide robust and light weight components at a lower cost. A Finite Element Analysis (FEA) based study aimed at optimising the electrical performance of a polymeric package for such power semiconductors is described in this paper. From the FEA simulations carried out, it was observed that one critical region where the electrical stresses tend to be high, and long-term failure may therefore occur, is in the contact region between the polymer housing and the metal inserts (flanges) which attach the housing to the copper pole pieces of the device. Different design features for the insert edge were studied in order to investigate their influence and to reduce the peak electrical field (E-field) in the critical region. The results showed that the E-field around the contact region decreased as the radii of curvature of the insert ends was increased. A comparison of the E-field magnitude for different insert designs also showed it to be lower around an elliptical insert end compared to circular and straight flange designs. Changes in the depth to which the flange protrudes inside the housing also had a significant effect in the electrical field magnitude in the contact region, whilst variation of other housing design parameters, such as the package thickness and the location of the insert relative to the housing periphery, did not cause the electric field to change significantly.
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