Guan‐Ying Huang

National Chung Hsing University

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Soon-Jyh Chang

National Cheng Kung University

Chun-Cheng Liu

MediaTek (Taiwan)

Ying-Zu Lin

MediaTek (Taiwan)

Ya-Ting Shyu

National Cheng Kung University

Chun-Po Huang

National Cheng Kung University

Chung-Ming Huang

National Yang Ming Chiao Tung University

Yin‐Tse Huang

University of Florida

Jie‐Hao Ou

National Chung Hsing University

Yun‐Shen Lu

Taiwan Agricultural Research Institute Council of Agriculture, Executive Yuan

Yu‐Hsuan Fan

National Taiwan University

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National Cheng Kung University

Kaohsiung Medical University

Himax (Taiwan)

National Chung Hsing University

National Taipei University

National Taiwan University

National Taiwan University of Science and Technology

Food Industry Research and Development Institute

Sun Yat-sen University

National Yang Ming Chiao Tung University

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A successive approximation ADC with resistor-capacitor hybrid structure

Ting-Zi Chen Soon-Jyh Chang Guan‐Ying Huang

This paper presents a 10-bit 50MS/s successive approximation register (SAR) ADC with low input capacitance that uses an on-chip resistive ladder to arrange a new switching scheme. The proposed arrangement not only reduces the total input capacitance, but also performs the predictive capacitor switching sequence to further reduce the power consumption. Therefore, the proposed SAR ADC has the features of small area and low power consumption. Compared to conventional SAR ADCs, the proposed ADC reduces the input capacitance to 512 fF for 10-bit resolution. This work is fabricated in TSMC 90-nm 1P9M CMOS process. This prototype chip consumes 0.703 mW from a 1.2-V supply and the ENOB is 9.3 bits at 50 MS/s sampling rate. The resultant FoM is 28 fJ/conversion-step.

Successive approximation ADC

Shaping

Low-power electronics

Resistive touchscreen

10.1109/vldi-dat.2013.6533842

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Citations (7)

90nm CMOSによる9ビット 150MS/s 1.53mW サブレンジ(subranged)SAR ADC

Symposium on VLSI Circuits (2010)

Lin Ying-Zu Chun-Cheng Liu Guan‐Ying Huang Ya-Ting Shyu Chang Soon-Jyh

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Establishing an Interactive Sequence Database for Shiitake Cultivar Identification

Journal of Basic Microbiology (2024)

Jie‐Hao Ou Han‐Yun Li Yun‐Shen Lu Chi‐Yu Chen Yu‐Hsuan Fan

ABSTRACT Shiitake mushrooms ( Lentinula edodes ) hold significant cultural and economic value, particularly in Asia where they are extensively cultivated. The diversification of shiitake cultivars, driven by the need to adapt to various climatic conditions and cultivation methods, has resulted in over 200 distinct cultivars. Reliable identification of these cultivars is crucial for breeding, intellectual property protection, and effective genetic resource management. Traditional morphological methods are inadequate due to their subjectivity and labor‐intensive nature. This study leverages nanopore high‐throughput sequencing to comprehensively analyze the rDNA regions (SSU, ITS, LSU, IGS) of 41 shiitake strains from Taiwan's Bioresource Collection and Research Center (BCRC), comprising 5 wild strains, 33 commercial strains, and 3 wild‐commercial hybrids. Our results identified the IGS1 region as the most variable and suitable for cultivar differentiation. Consequently, we developed an interactive online database ( https://github.com/Raingel/ShiitakeIGS1 ) that integrates 317 IGS1 sequences from Taiwan, Japan, and China. This platform allows users to upload their IGS1 sequences and identify similar cultivars through a user‐friendly interface, enhancing the precision and efficiency of shiitake cultivar identification.

Identification

10.1002/jobm.202400452

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A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS

Symposium on VLSI Circuits (2010)

Ying-Zu Lin Chun-Cheng Liu Guan‐Ying Huang Ya-Ting Shyu Soon-Jyh Chang

This paper reports a subranged SAR ADC consisting of a 3.5-bit flash coarse ADC, a 6-bit SAR fine ADC, and a differential segmented capacitive DAC. The flash ADC controls thermometer MSBs of the DAC and SAR ADC controls the binary LSBs. The segmented DAC improves DNL during MSB transitions. The merged switching of MSB capacitors enhances operation speed. The 9-bit 150-MS/s ADC consumes 1.53 mW from a 1.2-V supply. The ENOB is 8.69 bit and ERBW is 100 MHz. The FOMs at 1.2 V, 150 MS/s and 1 V, 100 MS/s are 24.7 and 17.7 fJ/conversion-step, respectively. At 1.3-V supply voltage, the sampling rate achieves 200 MS/s.

Successive approximation ADC

Flash ADC

Bit (key)

12-bit

10.1109/vlsic.2010.5560246

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Citations (51)

A 10b 100kS/s SAR ADC with charge recycling switching method

2022 IEEE Asian Solid-State Circuits Conference (A-SSCC) (2014)

Kai-Hsiang Chiang Soon-Jyh Chang Guan‐Ying Huang Ying-Zu Lin

This paper presents a low-voltage and energy-efficient 10b SAR ADC which manipulates charge recycling switching method for saving the switching energy. In additional, a window-based reconfigurable comparator is used to achieve fast comparison and small power dissipation. The proposed 10b SAR ADC operates at 100kS/s with 0.4V supply voltage in 90nm CMOS. The measurement results show that the prototype ADC achieve 55.37dB SNDR at Nyquist rate with only 107nW. The Figure-of-Merit (FoM) is 2.23fJ/conv.-step.

Successive approximation ADC

Figure of Merit

Flash ADC

Nyquist rate

10.1109/asscc.2014.7008927

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Citations (4)

A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications

IEEE Journal of Solid-State Circuits (2012)

Guan‐Ying Huang Soon-Jyh Chang Chun-Cheng Liu Ying-Zu Lin

This paper presents an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) for biomedical applications. To reduce energy consumption, a bypass window technique is used to select switching sequences to skip several conversion steps when the signal is within a predefined small window. The power consumptions of the capacitive digital-to-analog converter (DAC), latch comparator, and digital control circuit of the proposed ADC are lower than those of a conventional SAR ADC. The proposed bypass window tolerates the DAC settling error and comparator voltage offset in the first four phases and suppresses the peak DNL and INL values. A proof-of-concept prototype was fabricated in 0.18-μm 1P6M CMOS technology. At a 0.6-V supply voltage and a 200-kS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio of 57.97 dB and consumes 1.04 μW, resulting in a figure of merit of 8.03 fJ/conversion-step. The ADC core occupies an active area of only 0.082 mm ² .

Successive approximation ADC

Figure of Merit

12-bit

Flash ADC

Analog-to-digital converter

10.1109/jssc.2012.2217635

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Citations (132)

A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS

Ying-Zu Lin Soon-Jyh Chang Ya-Ting Shyu Guan‐Ying Huang Chun-Cheng Liu

This paper presents a new subrange analog-to-digital converter (ADC): a binary-search coarse ADC + a SAR fine ADC. The binary-search ADC improves conversion speed and gives coarse capacitors longer settling time. This ADC uses an RC hybrid DAC to reduce the unit capacitor count by 2. The rotation function of coarse capacitors enhances capacitor array linearity. The prototype in 90-nm CMOS only occupies an active area of 0.06 mm ² . From a 0.9-V supply, the power consumption is 0.32 and 0.58 mW at 10 and 25 MS/s, respectively. At 10 MS/s, the peak ENOB is 10.2 bit. At 25 MS/s, the peak ENOB is 9.9 bit and FOM is 29 fJ/conversion-step.

Successive approximation ADC

Linearity

10.1109/asscc.2011.6123606

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Citations (15)

A 10b 200MS/s 0.82mW SAR ADC in 40nm CMOS

2022 IEEE Asian Solid-State Circuits Conference (A-SSCC) (2013)

Guan‐Ying Huang Soon-Jyh Chang Ying-Zu Lin Chun-Cheng Liu Chun-Po Huang

This paper reports a successive-approximation analog-to-digital converter (ADC) which combines the bypass window and direct switching technique to tolerate the incomplete settling error and reduce the control logic delay. A small unit capacitor cell reduces the power consumption and settling time. The 10-bit prototype is fabricated in a 40nm CMOS process. At 200 MS/s and 0.9-V supply, this ADC consumes 0.82 mW and achieves an SNDR of 57.16 dB, resulting in an FOM of 13.9 fJ/Conversion-step.

Successive approximation ADC

Settling time

10.1109/asscc.2013.6691039

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Citations (16)

10-bit 30-MS/s SAR ADC Using a Switchback Switching Method

IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2012)

Guan‐Ying Huang Soon-Jyh Chang Chun-Cheng Liu Ying-Zu Lin

This brief presents a 10-bit 30-MS/s successive-approximation-register analog-to-digital converter (ADC) that uses a power efficient switchback switching method. With respect to the monotonic switching method, the input common-mode voltage variation reduces which improves the dynamic offset and the parasitic capacitance variation of the comparator. The proposed switchback switching method does not consume any power at the first digital-to-analog converter switching, which can reduce the power consumption and design effort of the reference buffer. The prototype was fabricated in a 90-nm 1P9M CMOS technology. At 1-V supply and 30 MS/s, the ADC achieves an sequenced neighbor double reservation of 56.89 dB and consumes 0.98 mW, resulting in a figure-of-merit (FOM) of 57 fJ/conversion-step. The ADC core occupies an active area of only 190 × 525 μm ² .

Successive approximation ADC

Figure of Merit

Parasitic capacitance

4-bit

Analog-to-digital converter

Shaping

10.1109/tvlsi.2012.2190117

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Citations (99)

Low power pipelined SAR ADC with loading-free architecture

Jia-Jhang Wu Soon-Jyh Chang Sheng-Hsiung Lin Chun-Po Huang Guan‐Ying Huang

This paper presents a 12-bit 70-MS/s pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with loading-free architecture. This work proposes a loading-free concept of merging the feedback capacitor and the capacitor array of the second-stage SAR ADC to reduce op-amp output loading and area. In addition, the fixed-window function technique is used to reduce the power consumption and tolerate non-idealities in the first-stage SAR ADC. The ADC core occupies an active area of 0.117 mm ² in TSMC 90-nm 1P9M CMOS process. The measured results shows that the proposed ADC achieves 55.98 dB SNDR with 2.72 mW power consumption at 1 MHz input frequency.

Successive approximation ADC

Shaping

Switched capacitor

10.1109/vlsi-dat.2014.6834906

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Citations (1)