Narges Attarmoghaddam

University of Victoria

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Kin Fun Li

University of Victoria

Saied Hosseini Khayat

Ferdowsi University of Mashhad

Mohammad Maymandi‐Nejad

Ferdowsi University of Mashhad

Awos Kanan

Princess Sumaya University for Technology

Cooperative Institutions

Ferdowsi University of Mashhad

University of Victoria

Washington University in St. Louis

Polytechnique Montréal

University of Waterloo

Princess Sumaya University for Technology

Government of Canada

Jordan University of Science and Technology

Xinjiang University

Hunan University

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An Area-Efficient FPGA Implementation of a Real-Time Multi-Class Classifier for Binary Images

IEEE Transactions on Circuits & Systems II Express Briefs (2022)

Narges Attarmoghaddam Kin Fun Li

Developing image classification modules in embedded systems is a complex task due to the limited resources available. In this brief, a multi-class image classifier using HOG feature extractor and SVM classifier is proposed for binary images. The novelty of the proposed system is applying two steps of binarization to the HOG technique to improve processing speed and area efficiency. First, HOG features are extracted from binary images to simplify the feature extraction process. Second, block normalization of the HOG is replaced with binarization to reduce hardware resource utilization. Compared to a similar existing work, our system speeds up the classification process while utilizing fewer hardware resources, with an 11.4% higher classification accuracy using the same setting.

Local Binary Patterns

Normalization

Extractor

Binary classification

Contextual image classification

10.1109/tcsii.2022.3148228

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Citations (12)

An Area-Efficient FPGA Implementation of a Real-Time Binary Object Detection System

Advances in intelligent systems and computing (2020)

Narges Attarmoghaddam Kin Fun Li

10.1007/978-3-030-57811-4_13

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Data Mining Hardware Acceleration for Object Detection

Narges Attarmoghaddam Kin Fun Li

Over the past decade, object detection has been an active research area in the field of computer vision due to its many applications such as intelligent robots, smart homes, monitoring and surveillance. The need for real-time detection in most of these applications and the frequent failure of software-based implementations in achieving real-time capability, has motivated researchers to utilize hardware acceleration. Due to the potential for parallelism, low power and reconfigurability, Field Programmable Gate Array (FPGA) devices are well-suited for object detection system implementation. In this survey, we investigate FPGA-based implementation of object detection systems using data mining algorithms.

Reconfigurability

Hardware acceleration

Implementation

Interface (matter)

10.1109/pacrim47961.2019.8985102

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Challenges and Methodologies of Hardware Security

Kin Fun Li Narges Attarmoghaddam

An attack on hardware typically results in a severer and difficult-to-recover damage, hence, it is our interest to focus this work on hardware security. A brief survey of security issues found in various application domains is presented, based on a collection of over seventy papers in IEEE Xplore archived since 2011. Challenges and potential solutions to different kinds of hardware attacks and threats are discussed. Finally, specific hardware security challenges are connected and mapped to each application domain.

Hardware security module

10.1109/aina.2018.00136

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FPGA Implementation of Crossover Module of Genetic Algorithm

Information (2019)

Narges Attarmoghaddam Kin Fun Li Awos Kanan

This paper proposes a hardware realization of the crossover module in the genetic algorithm for the travelling salesman problem (TSP). In order to enhance performance, we employ a combination of pipelining and parallelization with a genetic algorithm (GA) processor to improve processing speed, as compared to software implementation. Simulation results showed that the proposed architecture is six times faster than the similar existing architecture. The presented field-programmable gate array (FPGA) implementation of PMX crossover operator is more than 400 times faster than in software.

Realization (probability)

10.3390/info10060184

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FPGA implementation of power and area efficient compressed sensing for multi-channel ECG compression

Narges Attarmoghaddam Saied Hosseini Khayat Mohammad Maymandi‐Nejad

This paper presents the design of a low-power and area efficient hardware engine for multi-channel compression of electrocardiogram (ECG) signals. Compressed sensing (CS) is particularly well suited for low-power implementations because it can dramatically reduce circuit complexity for compression operations. We also present a CS architecture which allows power gating. Another feature of the proposed architecture is that it is suitable for multi-channel systems. The design is implemented in a certain family of FGPAs which are suited for low-power applications. Our measurement results show an effective reduction of power consumption between 20 to 40 percent at different operating frequencies using power gating technique. The power consumption of a 4-channel system and an 8-channel system is increased only by 7.1% and 11.2% respectively, compared to the single-channel system. The area of the 4-channel system and the 8-channel system compared to the single-channel system is increased only by a factor of 2.3 and 5.4, respectively.

Power gating

10.1109/iraniancee.2016.7585672

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Citations (3)