The switching time of a magnet in a spin current based majority gate depends on the input vector combination, and this often restricts the speed of majority-based circuits. To address this issue, this work proposes a novel two-phase scheme to implement majority logic and evaluates it on an all-spin logic (ASL) majority-based logic structures. In Phase 1, the output is initialized to a preset value. Next in Phase 2, the inputs are evaluated to switch the output magnet to its correct value. The time window for the output to switch in Phase 2 is fixed. Using such a scheme, an n-input AND gate which requires a total of (2n-1) inputs in the conventional implementation can now be implemented with only (n+1) inputs. When applied to standard logic functions, it is demonstrated that the proposed method of designing ASL gates are 1.6-3.4X faster and 1.9-6.9X more energy-efficient than the conventional method, and for a five-magnet full adder, it is shown that the proposed ASL implementation is 1.5X faster, 2.2X more energy-efficient, and provides a 16% improvement in area.
All-Spin Logic (ASL) devices provide a promising spintronics-based alternative for Boolean logic implementations in the post-Complementary Metal-Oxide Semiconductor (CMOS) era. In principle, any logic functionality can be implemented in ASL. In practice, the performance of an ASL gate is significantly affected by layout choices, but such implications have not been adequately explored in the past. This article proposes a systematic approach for building standard cells in ASL, which are a basic building block in an overall design methodology for implementing large ASL-based circuits. We first propose a new technique to reduce the magnet count for an ASL majority gate but still ensure correct functioning through layout optimization methods. Building on physics-based analysis, we then build a standard cell library with diverse functionality and characterize the library for delay, energy, and area. We perform delay-optimized technology mapping on ISCAS85 benchmark circuits using our library. Our approach results in circuits that are 12.90% faster, consume 26.16% less energy, and are 33.56% more area efficient compared to a standard cell library that does not incorporate layout-based optimization techniques of our work.
This work proposes CoMET, a fast and energy-efficient spintronics device for logic applications. An input voltage is applied to a ferroelectric (FE) material, in contact with a composite structure - a ferromagnet (FM) with in-plane magnetic anisotropy (IMA) placed on top of an intra-gate FM interconnect with perpendicular magnetic anisotropy (PMA). Through the magnetoelectric (ME) effect, the input voltage nucleates a domain wall (DW) at the input end of the PMA-FM interconnect. An applied current then rapidly propagates the DW towards the output FE structure, where the inverse-ME effect generates an output voltage. This voltage is propagated to the input of the next CoMET device using a novel circuit structure that enables efficient device cascading. The material parameters for CoMET are optimized by systematically exploring the impact of parameter choices on device performance. Simulations on a 7nm CoMET device show fast, low-energy operation, with a delay/energy of 98ps/68aJ for INV and 135ps/85aJ for MAJ3.
Many ultra-low power Internet of things (IoT) systems may be powered by energy harvested from ambient sources (e.g., solar radiation, thermal gradients, and WiFi). However, these energy sources can vary significantly in terms of their strengths and on/off patterns. For volatile systems, the intermittent nature of the energy sources necessitates the use of backup/recovery schemes to guarantee computational correctness and forward progress, which incur performance, area and energy overhead. Non-volatile (NV) processors based on spintronic devices, such as Spin-Transfer Torque (STT) memory and All-Spin-Logic (ASL), are more attractive alternatives. These NV devices are capable of achieving forward progress without relying on backup/recovery schemes. This work establishes a general framework for evaluating NV device-based processors for energy harvesting applications. Results demonstrate that NV spintronic processors can achieve significant energy savings (up to 83 x) versus a hybrid CMOS (computation) and STT-RAM (backup) implementation.
This work proposes CoMET, a fast and energy-efficient spintronics device for logic applications. An input voltage is applied to a ferroelectric (FE) material, in contact with a composite structure - a ferromagnet (FM) with in-plane magnetic anisotropy (IMA) placed on top of an intra-gate FM interconnect with perpendicular magnetic anisotropy (PMA). Through the magnetoelectric (ME) effect, the input voltage nucleates a domain wall (DW) at the input end of the PMA-FM interconnect. An applied current then rapidly propagates the DW towards the output FE structure, where the inverse-ME effect generates an output voltage. This voltage is propagated to the input of the next CoMET device using a novel circuit structure that enables efficient device cascading. The material parameters for CoMET are optimized by systematically exploring the impact of parameter choices on device performance. Simulations on a 7nm CoMET device show fast, low-energy operation, with a delay/energy of 98ps/68aJ for INV and 135ps/85aJ for MAJ3.
This work proposes a novel logic device (SkyLogic) based on skyrmions, which are magnetic vortex-like structures that have low depinning current density and are robust to defects. A charge current sent through a polarizer ferromagnet (P-FM) nucleates a skyrmion at the input end of an intra-gate FM interconnect with perpendicular magnetic anisotropy (PMA-FM). The output end of the PMA--FM forms the free layer of an MTJ stack. A spin Hall metal (SHM) is placed beneath the PMA-FM. The skyrmion is propagated to the output end of the PMA-FM by passing a charge current through the SHM. The resistance of the MTJ stack is low (high) when a skyrmion is present (absent) in the free layer, thereby realizing an inverter. A framework is developed to analyze the performance of the SkyLogic device. A circuit-level technique is developed that counters the transverse displacement of skyrmion in the PMA-FM and allows use of high current densities for fast propagation. The design space exploration of the PMA-FM material parameters is performed to obtain an optimal design point. At the optimal point, we obtain an inverter delay of 434 ps with a switching energy of 7.1 fJ.
The spin transfer torque magnetoresistive random access memory (STT-MRAM) is the leading candidate for spin-based memories. Nevertheless, the high write energy and read disturbance of the STT-MRAM motivated researchers to find other solutions. The spin Hall effect (SHE)-based MRAM is an alternative for the STT-MRAM, which also provides nonvolatility, zero leakage, and competitive area per bit, but with a lower write current. This paper focuses on a systematic performance analysis of these two proposed memory solutions. The SHE requires an external field to deterministically switch perpendicular magnetic anisotropy magnetic tunnel junction (MTJ). A previous experiment showed that the SHE can switch composite MTJ containing an in-plane layer without any field. In this paper, both traditional and composite MTJ structures are modeled in SPICE, which can reproduce realistic MTJ characteristics with user-defined input parameters. This self-contained model is used to compare the write energy and delay of the STT-MRAM and the SHE magnetoresistive random access memory (SHE-MRAM) for various write schemes including thermal fluctuation. Our simulations show, compared with the STT-MRAM, that the SHE-MRAM improves the write delay and the energy by eight times and seven times, respectively. Based on our extensive analysis incorporating the latest advances in magnetic materials and device technology, we predict that the SHE-MRAM is a feasible low-energy memory solution for future computing systems.
This paper proposes composite-input magnetoelectric-based logic technology (CoMET), a fast and energy-efficient spintronics device for logic applications. An input voltage is applied to a ferroelectric (FE) material, in contact with a composite structure—a ferromagnet (FM) with in-plane magnetic anisotropy placed on top of an intragate FM interconnect with perpendicular magnetic anisotropy (PMA). Through the magnetoelectric (ME) effect, the input voltage nucleates a domain wall (DW) at the input end of the PMA-FM interconnect. An applied current then rapidly propagates the DW toward the output FE structure, where the inverse-ME effect generates an output voltage. This voltage is propagated to the input of the next CoMET device using a novel circuit structure that enables efficient device cascading. The material parameters for CoMET are optimized by systematically exploring the impact of parameter choices on device performance. Simulations on a 7-nm CoMET device show fast, low-energy operation, with a delay/energy of 99 ps/68 aJ for INV and 135 ps/85 aJ for MAJ3.
The design of logic and memory circuits in emerging spintronics technology offers fertile ground for new ideas and innovations. We first describe methods for optimizing spintronic logic circuits at the level of physical design, including systematic approaches for building standard cell libraries to enable the design of large circuits. Next, we examine issues in the design of spintronic memories and present methods that trade off volatility with error correction to create dense memory arrays.
As we approach the limits of CMOS scaling, researchers are developing "beyond-CMOS" technologies to sustain the technological benefits associated with device scaling. Spin-tronic technologies have emerged as a promising beyond-CMOS technology due to their inherent benefits over CMOS such as high integration density, low leakage power, radiation hardness, and non-volatility. These benefits make spintronic devices an attractive successor to CMOS-especially for memory circuits. However, spintronic devices generally suffer from slower switching speeds and higher write energy, which limits their usability. In an effort to close the energy-delay gap between CMOS and spintronics, device concepts such as CoMET (Composite-Input Magnetoelectric-base Logic Technology) have been introduced, which collectively leverage material phenomena such as the spin-Hall effect and the magnetoelectric effect to enable fast, energy efficient device operation. In this work, we propose a non-volatile flip-flop (NVFF) based on CoMET technology that is capable of achieving up to two orders of magnitude less write energy than CMOS. This low write energy (≈2 aJ) makes our CoMET NVFF especially attractive to architectures that require frequent backup operations-e.g., for energy harvesting non-volatile processors.
'/%3e%3cuse xlink:href='%23a' transform='rotate(23.036 .093 25.536)'/%3e%3cuse xlink:href='%23a' transform='rotate(45.87 1.273 16.18)'/%3e%3cuse xlink:href='%23a' transform='rotate(69.945 .996 12.078)'/%3e%3cuse xlink:href='%23a' transform='rotate(20.66 -19.689 31.932)'/%3e%3c/svg%3e)
'%3e%3cg id='b'%3e%3cpath id='a' stroke='%23000' stroke-width='2' d='M-6-25H6m-12 3H6m-12 3H6'/%3e%3cuse xlink:href='%23a' y='44'/%3e%3c/g%3e%3cpath stroke='%23fff' d='M0 17v10'/%3e%3ccircle r='12' fill='%23cd2e3a'/%3e%3cpath fill='%230047a0' d='M0-12A6 6 0 0 0 0 0a6 6 0 0 1 0 12 12 12 0 0 1 0-24z'/%3e%3c/g%3e%3cg transform='rotate(-123.69)'%3e%3cuse xlink:href='%23b'/%3e%3cpath stroke='%23fff' d='M0-23.5v3M0 17v3.5m0 3v3'/%3e%3c/g%3e%3c/svg%3e)