In pursuit of thin film ferroelectric materials for frequency agile applications that are both easily adapted to large area deposition and also high performance, an investigation has been carried out into sol-gel deposition of 3% Mn doped (Pb0.4Sr0.6)TiO3. Large area capability has been demonstrated by growth of films with good crystallinity and grain structure on 4 in. Si wafers. Metal-insulator-metal capacitors have also been fabricated and development of an improved de-embedding technique that takes parasitic impedances fully into account has enabled accurate extraction of the high frequency dielectric properties of the PbxSr1−xTiO3 films. Practically useful values of ε∼1000, tan δ∼0.03, and tunability ∼50% have been obtained in the low gigahertz range (1–5 GHz). Peaks in the dielectric loss due to acoustic resonance have been modeled and tentatively identified as due to an electrostrictive effect with an electromechanical coupling coefficient of ∼0.04 at an electric field of 240 kV/cm which is potentially useful for tunable thin film bulk acoustic wave devices.
In this work, we describe how the frequency dependence of conductance (G) and capacitance (C) of a generic MOS capacitor results in peaks of the functions G/ω and - ωdC/dω. By means of TCAD simulations, we show that G/ω and -ωdC/dω peak at the same value and at the same frequency for every bias point from accumulation to inversion. We illustrate how the properties of the peaks change with the semiconductor doping (N D ), oxide capacitance (C OX ), minority carrier lifetime (τ g ), interface defect parameters (N IT , σ) and majority carrier dielectric relaxation time (τ r ). Finally, we demonstrate how these insights on G/ω and -ωdC/dω can be used to extract CO X , N D and τ g from InGaAs MOSCAP measurements.
A novel technique has been developed that is sensitive to the degree of voiding damage induced in a wide-line interconnect test structure. The technique is based on the measurement of the scattering parameters (S-parameters) of a simple metal-line test structure over a range of high frequencies. The transmission-line parameter, G (leakage conductance), which is calculated from the S-parameter measurements, is shown to be sensitive to distributed voiding, especially in wider lines. This is significant for the following reasons: (1) the measurement is fast, at a few seconds per test structure; (2) it can be performed at wafer level; (3) it does not rely on overstressing of the metallization; and (4) it is sensitive to the amount of voiding damage present in wide interconnect lines. Potential applications for this technique are: (a) an in-line statistical reliability control (SRC) test for the detection of stress voids induced during processing, and (b) an in-line SRC test for electromigration when preceded by a suitable current pre-stress step.
The integration of Schottky diode submillimetre wave circuits on GaAs membranes, and the transfer of the circuit to a lower dielectric membrane substrate is discussed. Two 366GHz mixers were designed to demonstrate the membrane approach using post processing of commercial foundry processed wafers.
Impedance spectroscopy of the metal-oxide semiconductor (MOS) system has played a central role in the development of silicon-based complementary MOS (CMOS) technology over the past 50 years [1, 2]. With current research interest into alternative semiconductor channels to silicon for MOSFET and tunnel FET technologies, the measurement and interpretation of the overall impedance of the MOS structure requires detailed analysis to separate and quantify the contribution of interface states, and near interface traps (border traps), on the capacitance and conductance response, and to separate the contribution of these electrically active defect states from the ac response of minority carriers in the case of genuine inversion of the semiconductor/dielectric interface. There has been considerable progress in recent years in reducing the interface state density (D it ) [3], [4], [5], in narrow gap In x Ga 1-x As MOS structures to the point where genuine surface inversion can be observed for both n- and p-type In 0.53 Ga 0.47 As MOS capacitors, which is confirmed by analysis of the minimum capacitance of n- and p-type In 0.53 Ga 0.47 As MOS structure with doping concentration ranging from approximately 1x10 16 to 1x10 18 cm -3 [6]. In this presentation we will provide an overview of the experimental relationship between specific functions of the capacitance (C) and conductance (G) for the case of narrow band gap III-V MOS structures which exhibit genuine surface inversion, where the capacitance and conductance of the MOS system as a function of ac angular frequency (ω) are related, and in particular, the peak values of G/ω and −dC/dlog e (ω) (≡− ωdC/dω) are equal, and that these peak magnitudes occur at the same value of ω [7]. The relationship is also confirmed by physics based ac simulations of MOS structures and through analysis of the equivalent circuit model in inversion. Results will be presented for InGaAs and InGaSb MOS structures (Al 2 O 3 and Al 2 O 3 /HfO 2 ALD oxides) where genuine inversion of the III-V/oxide surface is confirmed by the G/ω and −dC/dlog e (ω) functions, which have peak values of C ox 2 /2(C ox +C d ) when the surface is inverted (where C ox is the gate oxide capacitance and C d is the maximum capacitance of the semiconductor surface in inversion). In the case of p type InGaSb MOS structures it is also notable that the accumulation frequency dispersion is very low (<0.7%/decade) indicating a reduced density of border traps at energies in the Al 2 O 3 gate oxide aligning with the In 0.3 Ga 0.7 Sb valence band edge, which is approximately aligned with the lowest energy in the In 0.53 Ga 0.47 As conduction band gamma valley. Finally, experimental results and physics based simulations will be presented, which indicate that the peak values of G/ω and −dC/dlog e (ω) in inversion for any MOS system which demonstrates an inversion response within the typically range of temperatures and ac signal frequencies employed in experiments, opens a route to determine the gate oxide capacitance in inversion (where the gate oxide field and gate leakage are reduced), and that the angular frequency associated with the peak values of the G/ω and −dC/dlog e (ω) functions allows the determination of the minority carrier generation rate in the semiconductor, which is relevant to the leakage currents in MOSFETs and the optical performance in photonic applications. [1] E. H. Nicollian and J. R. Brews, MOS Physics and Technology. New York, NY, USA: Wiley, 1982 [2] E. H. Nicollian and A. Goetzberger, “The Si-SiO2 interface—Electrical properties as determined by the metal-insulator-silicon conductance technique,” Bell Syst. Tech. J., vol. 46, no. 6, pp. 1055–1133, 1967. [3] É. O’Connor et al., J. Appl. Phys., vol. 109, no. 2, p. 024101, 2011. [4] H.-D. Trinh et al., Appl. Phys. Lett., vol. 97, no. 4, pp. 042903-1–042903-3, 2010. [5] T. D. Lin et al., “Realization of high-quality HfO2 on In0.53Ga0.47As by in-situ atomic-layer-deposition,” Appl. Phys. Lett., vol. 100, no. 17, p. 172110, 2012. [6] E. O'Connor, K. Cherkaoui, S. Monaghan, B. Sheehan, I. M. Povey, and P. K. Hurley, Appl. Phys. Lett 110, 032902 (2017) [7] Scott Monaghan, Éamon O’Connor, Rafael Rios, Fahmida Ferdousi, Liam Floyd, Eimear Ryan, Karim Cherkaoui, Ian M. Povey, Kelin J. Kuhn, and Paul K. Hurley, IEEE Transaction on Electron Devices, 61, 4176 (2014)
Evidence of one-dimensional subband formation is found at low temperature in trigate silicon-on-insulator MOSFETs, resulting in oscillations of the I/sub D/(V/sub G/) characteristics. These oscillations correspond to the filling of energy subbands by electrons as the gate voltage is increased. High mobility, reaching 1200 cm/sup 2//Vs, is measured in the subbands at T=4.4 K. Subband mobility decreases as temperature is increased. Conduction in subbands disappears for temperatures higher than 100 K or for drain voltage values that are significantly larger than kT/q.
Arrays of 28 kDa nanocrystal gold molecules behave as weakly-coupled molecular solids comprising discrete nanoscale metallic islands separated by insulating ligand barriers. The key parameters which are found to dominate charge transport are (a) the single-electron nanocrystal charging energy, governed by the core diameter, the dielectric properties of the passivating ligands and classical electrostatic coupling between neighbouring cores; (b) the inter-nanocrystal tunnel barrier resistance that arises from the insulating nature of the ligand bilayers that separate the cores; and (c) the dimensionality of the network of current-carrying paths.
The electronic properties of metal nanocrystal quantum dot solids in the insulating state have been measured as a function of nanocrystal diameter under conditions of controlled inter-nanocrystal separation. Such properties of these weakly coupled nanocrystal arrays (see image), in particular the array charging energy, can be manipulated through experimental control of the nanocrystal diameter and mean inter-nanocrystal separation.
We present the development of a high-k first n-channel InGaAs metal-oxide-semiconductor field effect transistors (MOSFETs) and the effect of annealing on the source/drain (S/D) sheet resistance (R s ) and the high-k gate oxide. Test structures based on the transfer length method (TLM) were used as part of a design of experiment (DOE) to optimize the S/D implant activation process. The optimized process was 715°C for 32 s, leading to a minimum R s of (195.6 ± 3.4) Ω/d. Metal-oxide-semiconductor capacitors (MOSCAPs) with a 2 nm Al 2 O 3 /8 nm HfO 2 gate oxide were annealed at 675°C, 700°C and 725°C for 30 s. Leakage current lower than 2.1×10 -8 A/cm 2 were obtained for electric fields of ~3 MV/cm and low frequency dispersion of capacitance in accumulation (<;1.7%) were obtained. Densities of interface states (D IT ) were estimated using the conductance method. The output characteristics of a 5-μm gate length MOSFET annealed at 650°C is presented.
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