The current-voltage (I-V) characteristics of capacitors using SrTiO 3 film were investigated. Rectification characteristics were observed, either when oxygen gas was introduced during sputter deposition of top electrodes, or when the SrTiO 3 film was annealed in oxygen. These I-V characteristics are attributed to blocking contacts between SrTiO 3 and the electrodes. It is considered that such contacts are formed because of the reduction of the crystal defects in SrTiO 3 films, and they have decisive influence on the leakage current of the capacitor.
Abstract This study compiled the number of End-of-Life motorcycles (ELMCs), utilizing Japanese official motorcycle data to clarify “the characteristics of distribution flow and main actors” of ELMCs. Based on its results, domestic ELMCs were estimated at approximately between 500,000 and 600,000 annually. The exact ELMCs number in 2019 was 521,644, 81.4% of which were exported. The ratio of exported used motorcycles among these ELMCs was analyzed and categorized according to engine discharge. Accordingly, the analysis showed that motorcycles with 50 cc and less total emissions had a high proportion, 62.8%, of the total in 2019. New insights from this study include (1) the characteristics of the used motorcycle distribution flow in Japan and that they are eventually exported and (2) the main actors in the distribution flow are used motorcycle auction sites that assume a leading role in recycling motorcycles domestically and internationally.
Defects induced by B+ implantation (35 keV) at liquid-nitrogen (LN) temperature and −60 °C are examined using transmission electron microscopy (TEM), secondary-ion-mass spectroscopy, and electrical characterization of p+n diodes. B+ implantation at LN temperature produces a 120-nm-thick amorphous layer with a residual surface crystalline region. B+ implantation at −60 °C does not produce an amorphous layer, but damage can be observed as a dark band at the depth of B+ projected range Rp. For RT implantation, cross-sectional transmission electron microscopy reveals no visible damage in contrast to implantation at −60 °C. Frenkel-pair diffusion and annihilation is suppressed during implantation at the low temperature. The damage accumulates to form an amorphous layer for LN temperature. At −60 °C, the defects are confined near Rp. After annealing at 1000 °C for 10 min, near-surface and depth-encountering solid-phase-epitaxy dislocation-loop defects are observed in the sample implanted at LN temperature. The density of these is about several 108 cm−2, which is 10 or 100 times smaller than samples implanted at higher temperature. The annealed samples implanted at −60 °C and RT are mainly 〈111〉-plane directed defects and dislocation loops, respectively. Corresponding to the degree of as-implanted damage, the defects distribute at a shallower depth in the sample implanted at −60 °C than at RT, and have about 10 times higher density. The leakage current characteristics of p+n diodes indicate that the LN temperature and −60 °C implanted samples have lower leakage than RT samples at all annealing conditions. Notably, at 1000 °C for 10 min the leakage current is reduced to 56%. This is consistent with the result of TEM analysis; thus, the defect confinement to shallow layer by cooling contributes to lower the leakage current. Implantation at −60 °C is suitable for modern high-current implanters, due to practical coolant and less mechanical stress by thermoplasticity.
Performance requirements are soaring for embedded processors, whose demand in multimedia processing is rising now more than ever. Some DSP and media processors satisfy this by means of VLIW architecture. However, for embedded processors, less code, low power and small die are compulsory. These requirements make 4-way super-scalar embedded processor impractical. This embedded processor utilizes 4-way VLIW architecture characterized by: (1) parallel execution by VLIW. (2) generic CPU function in combination with media processing function for enhancing multimedia processing ability. (3) NOP instruction suppressing by packing flags for compatibility among different parallel levels. (4) two parallel execution mechanisms, ILP and SIMD.
